2043 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \  argument
2054 #define MG_TX1_LINK_PARAMS(ln, tc_port) \  argument
2067 #define MG_TX2_LINK_PARAMS(ln, tc_port) \  argument
2081 #define MG_TX1_PISO_READLOAD(ln, tc_port) \  argument
2094 #define MG_TX2_PISO_READLOAD(ln, tc_port) \  argument
2108 #define MG_TX1_SWINGCTRL(ln, tc_port) \  argument
2121 #define MG_TX2_SWINGCTRL(ln, tc_port) \  argument
2136 #define MG_TX1_DRVCTRL(ln, tc_port) \  argument
2149 #define MG_TX2_DRVCTRL(ln, tc_port) \  argument
2169 #define MG_CLKHUB(ln, tc_port) \  argument
2183 #define MG_TX1_DCC(ln, tc_port) \  argument
2195 #define MG_TX2_DCC(ln, tc_port) \  argument
2211 #define MG_DP_MODE(ln, tc_port)	\  argument
10536 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \  argument
10611 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \  argument
10622 #define ADLP_PORTTC_PLL_ENABLE(tc_port)		_MMIO_PORT((tc_port), \  argument
10632 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \  argument
10644 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \  argument
10664 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \  argument
10678 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \  argument
10693 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \  argument
10706 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \  argument
10719 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \  argument
10733 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \  argument
10753 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \  argument
10765 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \  argument
10881 #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10890 #define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10902 #define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10911 #define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10920 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \  argument
10927 #define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \  argument
10934 #define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \  argument
10941 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \  argument
10953 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \  argument
10960 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \  argument
10968 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \  argument
10975 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \  argument
10981 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \  argument
10987 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \  argument
10993 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \  argument
10999 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \  argument
11006 #define DKL_CMN_UC_DW_27(tc_port)		_MMIO(_PORT(tc_port, \  argument
11019 #define HIP_INDEX_REG(tc_port)		_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \  argument
11021 #define _HIP_INDEX_SHIFT(tc_port)	(8 * ((tc_port) % 4))  argument
11022 #define HIP_INDEX_VAL(tc_port, val)	((val) << _HIP_INDEX_SHIFT(tc_port))  argument