Lines Matching +full:sub +full:- +full:sampled
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
11 * distribute, sub license, and/or sell copies of the Software, and to
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); in pmu_irq_stats()
184 struct i915_hotplug *hpd = &dev_priv->hotplug; in intel_hpd_init_pins()
189 hpd->hpd = hpd_status_g4x; in intel_hpd_init_pins()
191 hpd->hpd = hpd_status_i915; in intel_hpd_init_pins()
196 hpd->hpd = hpd_gen11; in intel_hpd_init_pins()
198 hpd->hpd = hpd_bxt; in intel_hpd_init_pins()
200 hpd->hpd = hpd_bdw; in intel_hpd_init_pins()
202 hpd->hpd = hpd_ivb; in intel_hpd_init_pins()
204 hpd->hpd = hpd_ilk; in intel_hpd_init_pins()
211 hpd->pch_hpd = hpd_sde_dg1; in intel_hpd_init_pins()
213 hpd->pch_hpd = hpd_icp; in intel_hpd_init_pins()
215 hpd->pch_hpd = hpd_spt; in intel_hpd_init_pins()
217 hpd->pch_hpd = hpd_cpt; in intel_hpd_init_pins()
219 hpd->pch_hpd = hpd_ibx; in intel_hpd_init_pins()
229 drm_crtc_handle_vblank(&crtc->base); in intel_handle_vblank()
271 drm_WARN(&uncore->i915->drm, 1, in gen3_assert_iir_is_zero()
287 drm_WARN(&uncore->i915->drm, 1, in gen2_assert_iir_is_zero()
326 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
327 drm_WARN_ON(&dev_priv->drm, bits & ~mask); in i915_hotplug_interrupt_update_locked()
329 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
332 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val); in i915_hotplug_interrupt_update_locked()
336 * i915_hotplug_interrupt_update - update hotplug interrupt enable
341 * of an interrupt context. To avoid that read-modify-write cycles
344 * held already, this function acquires the lock itself. A non-locking
351 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
353 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
357 * ilk_update_display_irq - update DEIMR
368 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
369 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ilk_update_display_irq()
371 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
375 if (new_val != dev_priv->irq_mask && in ilk_update_display_irq()
376 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { in ilk_update_display_irq()
377 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
378 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
379 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); in ilk_update_display_irq()
384 * bdw_update_port_irq - update DE port interrupt
396 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_port_irq()
398 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_port_irq()
400 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
403 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
410 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
411 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
416 * bdw_update_pipe_irq - update DE pipe interrupt
429 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_pipe_irq()
431 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_pipe_irq()
433 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_pipe_irq()
436 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
440 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
441 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
442 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
443 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
448 * ibx_display_interrupt_update - update SDEIMR
457 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
461 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ibx_display_interrupt_update()
463 lockdep_assert_held(&dev_priv->irq_lock); in ibx_display_interrupt_update()
465 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
468 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); in ibx_display_interrupt_update()
469 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
475 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
478 lockdep_assert_held(&dev_priv->irq_lock); in i915_pipestat_enable_mask()
487 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
494 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
507 drm_WARN_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
522 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_enable_pipestat()
526 lockdep_assert_held(&dev_priv->irq_lock); in i915_enable_pipestat()
527 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
529 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
532 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
535 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_enable_pipestat()
536 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_enable_pipestat()
545 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_disable_pipestat()
549 lockdep_assert_held(&dev_priv->irq_lock); in i915_disable_pipestat()
550 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
552 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
555 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
558 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_disable_pipestat()
559 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_disable_pipestat()
564 if (!dev_priv->opregion.asle) in i915_has_asle()
571 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
579 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
586 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
606 * | may be shifted forward 1-3 extra lines via PIPECONF
613 * ----va---> <-----------------vb--------------------> <--------va-------------
614 * | | <----vs-----> |
615 …* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter …
616 …* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter …
617 …* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter …
632 * - most events happen at the start of horizontal sync
633 * - frame start happens at the start of horizontal blank, 1-4 lines
635 * - gen3/4 pixel and frame counter are synchronized with the start
644 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915_get_vblank_counter()
645 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; in i915_get_vblank_counter()
646 const struct drm_display_mode *mode = &vblank->hwmode; in i915_get_vblank_counter()
647 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i915_get_vblank_counter()
659 * does not like us returning non-zero frame counter values in i915_get_vblank_counter()
661 * counter. Thus we must stop non-zero values leaking out. in i915_get_vblank_counter()
663 if (!vblank->max_vblank_count) in i915_get_vblank_counter()
666 htotal = mode->crtc_htotal; in i915_get_vblank_counter()
667 hsync_start = mode->crtc_hsync_start; in i915_get_vblank_counter()
668 vbl_start = mode->crtc_vblank_start; in i915_get_vblank_counter()
669 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in i915_get_vblank_counter()
676 vbl_start -= htotal - hsync_start; in i915_get_vblank_counter()
681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
694 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
710 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in g4x_get_vblank_counter()
711 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; in g4x_get_vblank_counter()
712 enum pipe pipe = to_intel_crtc(crtc)->pipe; in g4x_get_vblank_counter()
714 if (!vblank->max_vblank_count) in g4x_get_vblank_counter()
717 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_scanlines_since_frame_timestamp()
724 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in intel_crtc_scanlines_since_frame_timestamp()
725 const struct drm_display_mode *mode = &vblank->hwmode; in intel_crtc_scanlines_since_frame_timestamp()
726 u32 htotal = mode->crtc_htotal; in intel_crtc_scanlines_since_frame_timestamp()
727 u32 clock = mode->crtc_clock; in intel_crtc_scanlines_since_frame_timestamp()
740 * is sampled at every start of vertical blank. in intel_crtc_scanlines_since_frame_timestamp()
743 PIPE_FRMTMSTMP(crtc->pipe)); in intel_crtc_scanlines_since_frame_timestamp()
752 PIPE_FRMTMSTMP(crtc->pipe)); in intel_crtc_scanlines_since_frame_timestamp()
755 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, in intel_crtc_scanlines_since_frame_timestamp()
770 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline_from_timestamp()
771 const struct drm_display_mode *mode = &vblank->hwmode; in __intel_get_crtc_scanline_from_timestamp()
772 u32 vblank_start = mode->crtc_vblank_start; in __intel_get_crtc_scanline_from_timestamp()
773 u32 vtotal = mode->crtc_vtotal; in __intel_get_crtc_scanline_from_timestamp()
777 scanline = min(scanline, vtotal - 1); in __intel_get_crtc_scanline_from_timestamp()
789 struct drm_device *dev = crtc->base.dev; in __intel_get_crtc_scanline()
793 enum pipe pipe = crtc->pipe; in __intel_get_crtc_scanline()
796 if (!crtc->active) in __intel_get_crtc_scanline()
799 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline()
800 mode = &vblank->hwmode; in __intel_get_crtc_scanline()
802 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) in __intel_get_crtc_scanline()
805 vtotal = mode->crtc_vtotal; in __intel_get_crtc_scanline()
806 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in __intel_get_crtc_scanline()
843 return (position + crtc->scanline_offset) % vtotal; in __intel_get_crtc_scanline()
852 struct drm_device *dev = _crtc->dev; in i915_get_crtc_scanoutpos()
855 enum pipe pipe = crtc->pipe; in i915_get_crtc_scanoutpos()
861 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; in i915_get_crtc_scanoutpos()
863 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { in i915_get_crtc_scanoutpos()
864 drm_dbg(&dev_priv->drm, in i915_get_crtc_scanoutpos()
870 htotal = mode->crtc_htotal; in i915_get_crtc_scanoutpos()
871 hsync_start = mode->crtc_hsync_start; in i915_get_crtc_scanoutpos()
872 vtotal = mode->crtc_vtotal; in i915_get_crtc_scanoutpos()
873 vbl_start = mode->crtc_vblank_start; in i915_get_crtc_scanoutpos()
874 vbl_end = mode->crtc_vblank_end; in i915_get_crtc_scanoutpos()
876 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in i915_get_crtc_scanoutpos()
887 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
895 if (crtc->mode_flags & I915_MODE_FLAG_VRR) { in i915_get_crtc_scanoutpos()
907 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1); in i915_get_crtc_scanoutpos()
935 position = vtotal - 1; in i915_get_crtc_scanoutpos()
944 * always add htotal-hsync_start to the current pixel position. in i915_get_crtc_scanoutpos()
946 position = (position + htotal - hsync_start) % vtotal; in i915_get_crtc_scanoutpos()
955 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
964 position -= vbl_end; in i915_get_crtc_scanoutpos()
966 position += vtotal - vbl_end; in i915_get_crtc_scanoutpos()
973 *hpos = position - (*vpos * htotal); in i915_get_crtc_scanoutpos()
989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_get_crtc_scanline()
993 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1001 * ivb_parity_work - Workqueue called when a parity error interrupt
1013 struct intel_gt *gt = &dev_priv->gt; in ivb_parity_work()
1023 mutex_lock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
1026 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
1029 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1030 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivb_parity_work()
1031 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1033 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivb_parity_work()
1036 slice--; in ivb_parity_work()
1037 if (drm_WARN_ON_ONCE(&dev_priv->drm, in ivb_parity_work()
1041 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivb_parity_work()
1045 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
1050 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); in ivb_parity_work()
1051 intel_uncore_posting_read(&dev_priv->uncore, reg); in ivb_parity_work()
1060 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, in ivb_parity_work()
1063 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", in ivb_parity_work()
1072 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
1075 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
1076 spin_lock_irq(>->irq_lock); in ivb_parity_work()
1078 spin_unlock_irq(>->irq_lock); in ivb_parity_work()
1080 mutex_unlock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
1231 drm_dbg(&dev_priv->drm, in intel_get_hpd_pins()
1243 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_enabled_irqs()
1244 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) in intel_hpd_enabled_irqs()
1245 enabled_irqs |= hpd[encoder->hpd_pin]; in intel_hpd_enabled_irqs()
1256 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_hotplug_irqs()
1257 hotplug_irqs |= hpd[encoder->hpd_pin]; in intel_hpd_hotplug_irqs()
1268 for_each_intel_encoder(&i915->drm, encoder) in intel_hpd_hotplug_enables()
1269 hotplug |= hotplug_enables(i915, encoder->hpd_pin); in intel_hpd_hotplug_enables()
1276 wake_up_all(&dev_priv->gmbus_wait_queue); in gmbus_irq_handler()
1281 wake_up_all(&dev_priv->gmbus_wait_queue); in dp_aux_irq_handler()
1292 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; in display_pipe_crc_irq_handler()
1297 spin_lock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1306 if (pipe_crc->skipped <= 0 || in display_pipe_crc_irq_handler()
1307 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
1308 pipe_crc->skipped++; in display_pipe_crc_irq_handler()
1309 spin_unlock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1312 spin_unlock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1314 drm_crtc_add_crc_entry(&crtc->base, true, in display_pipe_crc_irq_handler()
1315 drm_crtc_accurate_vblank_count(&crtc->base), in display_pipe_crc_irq_handler()
1331 struct drm_crtc_state *crtc_state = crtc->base.state; in flip_done_handler()
1332 struct drm_pending_vblank_event *e = crtc_state->event; in flip_done_handler()
1333 struct drm_device *dev = &i915->drm; in flip_done_handler()
1336 spin_lock_irqsave(&dev->event_lock, irqflags); in flip_done_handler()
1338 crtc_state->event = NULL; in flip_done_handler()
1340 drm_crtc_send_vblank_event(&crtc->base, e); in flip_done_handler()
1342 spin_unlock_irqrestore(&dev->event_lock, irqflags); in flip_done_handler()
1349 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1357 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1360 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1370 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1375 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1380 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1381 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1382 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1391 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
1395 dev_priv->pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
1404 spin_lock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1406 if (!dev_priv->display_irqs_enabled) { in i9xx_pipestat_irq_ack()
1407 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1439 status_mask |= dev_priv->pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
1445 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
1458 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
1459 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); in i9xx_pipestat_irq_ack()
1462 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1578 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; in i9xx_hpd_irq_ack()
1584 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); in i9xx_hpd_irq_ack()
1587 drm_WARN_ONCE(&dev_priv->drm, 1, in i9xx_hpd_irq_ack()
1589 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); in i9xx_hpd_irq_ack()
1609 dev_priv->hotplug.hpd, in i9xx_hpd_irq_handler()
1630 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1638 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
1639 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); in valleyview_irq_handler()
1640 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
1654 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. in valleyview_irq_handler()
1660 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_handler()
1661 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in valleyview_irq_handler()
1662 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in valleyview_irq_handler()
1665 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); in valleyview_irq_handler()
1667 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); in valleyview_irq_handler()
1685 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in valleyview_irq_handler()
1687 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in valleyview_irq_handler()
1688 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_handler()
1691 gen6_gt_irq_handler(&dev_priv->gt, gt_iir); in valleyview_irq_handler()
1693 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); in valleyview_irq_handler()
1703 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1717 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1725 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
1726 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
1740 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. in cherryview_irq_handler()
1746 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
1747 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in cherryview_irq_handler()
1748 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in cherryview_irq_handler()
1750 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); in cherryview_irq_handler()
1769 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in cherryview_irq_handler()
1771 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in cherryview_irq_handler()
1772 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
1782 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1798 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_irq_handler()
1807 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in ibx_hpd_irq_handler()
1813 dev_priv->hotplug.pch_hpd, in ibx_hpd_irq_handler()
1829 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", in ibx_irq_handler()
1840 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); in ibx_irq_handler()
1843 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); in ibx_irq_handler()
1846 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in ibx_irq_handler()
1850 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
1852 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
1856 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); in ibx_irq_handler()
1859 drm_dbg(&dev_priv->drm, in ibx_irq_handler()
1871 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); in ivb_err_int_handler()
1875 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ivb_err_int_handler()
1889 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); in ivb_err_int_handler()
1894 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); in cpt_serr_int_handler()
1898 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in cpt_serr_int_handler()
1904 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); in cpt_serr_int_handler()
1917 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", in cpt_irq_handler()
1928 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); in cpt_irq_handler()
1931 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); in cpt_irq_handler()
1935 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
1937 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
1953 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_irq_handler()
1954 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg); in icp_irq_handler()
1958 dev_priv->hotplug.pch_hpd, in icp_irq_handler()
1965 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_irq_handler()
1966 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg); in icp_irq_handler()
1970 dev_priv->hotplug.pch_hpd, in icp_irq_handler()
1991 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_irq_handler()
1992 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in spt_irq_handler()
1996 dev_priv->hotplug.pch_hpd, in spt_irq_handler()
2003 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_irq_handler()
2004 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg); in spt_irq_handler()
2008 dev_priv->hotplug.pch_hpd, in spt_irq_handler()
2024 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_irq_handler()
2025 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); in ilk_hpd_irq_handler()
2029 dev_priv->hotplug.hpd, in ilk_hpd_irq_handler()
2051 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ilk_display_irq_handler()
2069 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ilk_display_irq_handler()
2077 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ilk_display_irq_handler()
2081 gen5_rps_irq_handler(&dev_priv->gt.rps); in ilk_display_irq_handler()
2099 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in ivb_display_irq_handler()
2102 u32 psr_iir = intel_uncore_read(&dev_priv->uncore, in ivb_display_irq_handler()
2106 intel_uncore_write(&dev_priv->uncore, in ivb_display_irq_handler()
2128 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ivb_display_irq_handler()
2133 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ivb_display_irq_handler()
2139 * 1 - Disable Master Interrupt Control.
2140 * 2 - Find the source(s) of the interrupt.
2141 * 3 - Clear the Interrupt Identity bits (IIR).
2142 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2143 * 5 - Re-enable Master Interrupt Control.
2148 void __iomem * const regs = i915->uncore.regs; in ilk_irq_handler()
2156 disable_rpm_wakeref_asserts(&i915->runtime_pm); in ilk_irq_handler()
2178 gen6_gt_irq_handler(&i915->gt, gt_iir); in ilk_irq_handler()
2180 gen5_gt_irq_handler(&i915->gt, gt_iir); in ilk_irq_handler()
2198 gen6_rps_irq_handler(&i915->gt.rps, pm_iir); in ilk_irq_handler()
2210 enable_rpm_wakeref_asserts(&i915->runtime_pm); in ilk_irq_handler()
2220 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_irq_handler()
2221 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in bxt_hpd_irq_handler()
2225 dev_priv->hotplug.hpd, in bxt_hpd_irq_handler()
2240 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2241 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2245 dev_priv->hotplug.hpd, in gen11_hpd_irq_handler()
2252 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2253 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2257 dev_priv->hotplug.hpd, in gen11_hpd_irq_handler()
2264 drm_err(&dev_priv->drm, in gen11_hpd_irq_handler()
2335 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in gen8_de_misc_irq_handler()
2339 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder); in gen8_de_misc_irq_handler()
2343 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg); in gen8_de_misc_irq_handler()
2344 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir); in gen8_de_misc_irq_handler()
2358 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); in gen8_de_misc_irq_handler()
2373 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); in gen11_dsi_te_interrupt_handler()
2385 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2389 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); in gen11_dsi_te_interrupt_handler()
2394 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2406 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
2414 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_te_interrupt_handler()
2415 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_te_interrupt_handler()
2444 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); in gen8_de_irq_handler()
2447 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); in gen8_de_irq_handler()
2449 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); in gen8_de_irq_handler()
2453 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2459 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); in gen8_de_irq_handler()
2461 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); in gen8_de_irq_handler()
2465 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2471 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); in gen8_de_irq_handler()
2475 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); in gen8_de_irq_handler()
2515 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2519 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2529 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
2531 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2537 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
2553 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2564 * on older pch-split platforms. But this needs testing. in gen8_de_irq_handler()
2566 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in gen8_de_irq_handler()
2568 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); in gen8_de_irq_handler()
2582 drm_dbg(&dev_priv->drm, in gen8_de_irq_handler()
2611 void __iomem * const regs = dev_priv->uncore.regs; in gen8_irq_handler()
2623 /* Find, queue (onto bottom-halves), then clear each source */ in gen8_irq_handler()
2624 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); in gen8_irq_handler()
2628 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2630 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2643 void __iomem * const regs = gt->uncore->regs; in gen11_gu_misc_irq_ack()
2660 intel_opregion_asle_intr(gt->i915); in gen11_gu_misc_irq_handler()
2684 void __iomem * const regs = i915->uncore.regs; in gen11_display_irq_handler()
2687 disable_rpm_wakeref_asserts(&i915->runtime_pm); in gen11_display_irq_handler()
2697 enable_rpm_wakeref_asserts(&i915->runtime_pm); in gen11_display_irq_handler()
2703 void __iomem * const regs = i915->uncore.regs; in gen11_irq_handler()
2704 struct intel_gt *gt = &i915->gt; in gen11_irq_handler()
2717 /* Find, queue (onto bottom-halves), then clear each source */ in gen11_irq_handler()
2760 struct intel_gt *gt = &i915->gt; in dg1_irq_handler()
2761 void __iomem * const regs = i915->uncore.regs; in dg1_irq_handler()
2805 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_enable_vblank()
2806 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank()
2809 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2811 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2818 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_enable_vblank()
2822 * Disabling render clock gating during C-states avoids in i915gm_enable_vblank()
2826 if (dev_priv->vblank_enabled++ == 0) in i915gm_enable_vblank()
2827 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
2834 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_enable_vblank()
2835 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank()
2838 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2841 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2848 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_enable_vblank()
2849 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank()
2854 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2856 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2870 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in gen11_dsi_configure_te()
2874 if (!(intel_crtc->mode_flags & in gen11_dsi_configure_te()
2879 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) in gen11_dsi_configure_te()
2884 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port)); in gen11_dsi_configure_te()
2890 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp); in gen11_dsi_configure_te()
2892 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_configure_te()
2893 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_configure_te()
2901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_enable_vblank()
2902 enum pipe pipe = crtc->pipe; in bdw_enable_vblank()
2908 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2910 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2916 drm_crtc_vblank_restore(&crtc->base); in bdw_enable_vblank()
2926 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_disable_vblank()
2927 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank()
2930 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2932 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2937 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_disable_vblank()
2941 if (--dev_priv->vblank_enabled == 0) in i915gm_disable_vblank()
2942 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)… in i915gm_disable_vblank()
2947 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_disable_vblank()
2948 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank()
2951 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2954 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2959 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_disable_vblank()
2960 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank()
2965 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2967 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2973 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_disable_vblank()
2974 enum pipe pipe = crtc->pipe; in bdw_disable_vblank()
2980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
2982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
2987 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_reset()
2995 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); in ibx_irq_reset()
3000 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_reset()
3008 …intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_ST… in vlv_display_irq_reset()
3013 dev_priv->irq_mask = ~0u; in vlv_display_irq_reset()
3018 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_postinstall()
3040 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
3042 dev_priv->irq_mask = ~enable_mask; in vlv_display_irq_postinstall()
3044 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
3051 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_reset()
3054 dev_priv->irq_mask = ~0u; in ilk_irq_reset()
3064 gen5_gt_irq_reset(&dev_priv->gt); in ilk_irq_reset()
3071 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_reset()
3072 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_reset()
3074 gen5_gt_irq_reset(&dev_priv->gt); in valleyview_irq_reset()
3076 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3077 if (dev_priv->display_irqs_enabled) in valleyview_irq_reset()
3079 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3084 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_display_irq_reset()
3104 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_reset()
3106 gen8_master_intr_disable(dev_priv->uncore.regs); in gen8_irq_reset()
3108 gen8_gt_irq_reset(&dev_priv->gt); in gen8_irq_reset()
3119 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_display_irq_reset()
3162 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_reset()
3164 gen11_master_intr_disable(dev_priv->uncore.regs); in gen11_irq_reset()
3166 gen11_gt_irq_reset(&dev_priv->gt); in gen11_irq_reset()
3175 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_reset()
3177 dg1_master_intr_disable(dev_priv->uncore.regs); in dg1_irq_reset()
3179 gen11_gt_irq_reset(&dev_priv->gt); in dg1_irq_reset()
3189 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_post_enable()
3195 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3198 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3204 dev_priv->de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
3205 ~dev_priv->de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
3207 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3213 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_pre_disable()
3216 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3219 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3226 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3234 struct intel_uncore *uncore = &dev_priv->uncore; in cherryview_irq_reset()
3236 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
3237 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
3239 gen8_gt_irq_reset(&dev_priv->gt); in cherryview_irq_reset()
3243 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3244 if (dev_priv->display_irqs_enabled) in cherryview_irq_reset()
3246 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3283 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_detection_setup()
3292 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in ibx_hpd_detection_setup()
3299 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in ibx_hpd_irq_setup()
3300 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in ibx_hpd_irq_setup()
3341 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_ddi_hpd_detection_setup()
3347 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug); in icp_ddi_hpd_detection_setup()
3354 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_tc_hpd_detection_setup()
3362 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug); in icp_tc_hpd_detection_setup()
3369 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in icp_hpd_irq_setup()
3370 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in icp_hpd_irq_setup()
3373 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in icp_hpd_irq_setup()
3401 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in dg1_hpd_irq_setup()
3406 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in dg1_hpd_irq_setup()
3415 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_tc_hpd_detection_setup()
3423 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug); in gen11_tc_hpd_detection_setup()
3430 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_tbt_hpd_detection_setup()
3438 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug); in gen11_tbt_hpd_detection_setup()
3446 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in gen11_hpd_irq_setup()
3447 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in gen11_hpd_irq_setup()
3449 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3452 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val); in gen11_hpd_irq_setup()
3453 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3496 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in spt_hpd_detection_setup()
3499 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in spt_hpd_detection_setup()
3503 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_hpd_detection_setup()
3509 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in spt_hpd_detection_setup()
3511 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_hpd_detection_setup()
3514 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug); in spt_hpd_detection_setup()
3522 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in spt_hpd_irq_setup()
3524 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in spt_hpd_irq_setup()
3525 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in spt_hpd_irq_setup()
3553 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_detection_setup()
3557 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); in ilk_hpd_detection_setup()
3564 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in ilk_hpd_irq_setup()
3565 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in ilk_hpd_irq_setup()
3607 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_detection_setup()
3615 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in bxt_hpd_detection_setup()
3622 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in bxt_hpd_irq_setup()
3623 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in bxt_hpd_irq_setup()
3632 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3643 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_postinstall()
3661 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_postinstall()
3692 dev_priv->irq_mask = ~display_mask; in ilk_irq_postinstall()
3696 gen5_gt_irq_postinstall(&dev_priv->gt); in ilk_irq_postinstall()
3698 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, in ilk_irq_postinstall()
3704 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
3706 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
3709 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
3719 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
3721 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
3724 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
3733 gen5_gt_irq_postinstall(&dev_priv->gt); in valleyview_irq_postinstall()
3735 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3736 if (dev_priv->display_irqs_enabled) in valleyview_irq_postinstall()
3738 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3740 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_postinstall()
3741 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_postinstall()
3746 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_de_irq_postinstall()
3802 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3807 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3826 struct intel_uncore *uncore = &dev_priv->uncore; in icp_irq_postinstall()
3839 gen8_gt_irq_postinstall(&dev_priv->gt); in gen8_irq_postinstall()
3842 gen8_master_intr_enable(dev_priv->uncore.regs); in gen8_irq_postinstall()
3852 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in gen11_de_irq_postinstall()
3858 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_postinstall()
3864 gen11_gt_irq_postinstall(&dev_priv->gt); in gen11_irq_postinstall()
3869 gen11_master_intr_enable(uncore->regs); in gen11_irq_postinstall()
3870 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); in gen11_irq_postinstall()
3875 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_postinstall()
3878 gen11_gt_irq_postinstall(&dev_priv->gt); in dg1_irq_postinstall()
3885 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in dg1_irq_postinstall()
3889 dg1_master_intr_enable(dev_priv->uncore.regs); in dg1_irq_postinstall()
3890 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR); in dg1_irq_postinstall()
3895 gen8_gt_irq_postinstall(&dev_priv->gt); in cherryview_irq_postinstall()
3897 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3898 if (dev_priv->display_irqs_enabled) in cherryview_irq_postinstall()
3900 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3902 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
3903 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
3908 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_reset()
3913 dev_priv->irq_mask = ~0u; in i8xx_irq_reset()
3918 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_postinstall()
3927 dev_priv->irq_mask = in i8xx_irq_postinstall()
3938 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
3940 /* Interrupt setup is already guaranteed to be single-threaded, this is in i8xx_irq_postinstall()
3942 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3945 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3951 struct intel_uncore *uncore = &i915->uncore; in i8xx_error_irq_ack()
3984 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", in i8xx_error_irq_handler()
3993 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
3995 intel_uncore_write(&dev_priv->uncore, EIR, *eir); in i9xx_error_irq_ack()
3997 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
4011 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
4012 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); in i9xx_error_irq_ack()
4013 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); in i9xx_error_irq_ack()
4022 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", in i9xx_error_irq_handler()
4035 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
4042 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
4055 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
4058 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i8xx_irq_handler()
4068 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
4075 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_reset()
4079 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i915_irq_reset()
4085 dev_priv->irq_mask = ~0u; in i915_irq_reset()
4090 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_postinstall()
4093 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE | in i915_irq_postinstall()
4097 dev_priv->irq_mask = in i915_irq_postinstall()
4114 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
4117 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
4119 /* Interrupt setup is already guaranteed to be single-threaded, this is in i915_irq_postinstall()
4121 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4124 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4138 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
4146 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
4163 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i915_irq_handler()
4166 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i915_irq_handler()
4179 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
4186 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_reset()
4189 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i965_irq_reset()
4194 dev_priv->irq_mask = ~0u; in i965_irq_reset()
4199 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_postinstall()
4216 intel_uncore_write(&dev_priv->uncore, EMR, error_mask); in i965_irq_postinstall()
4219 dev_priv->irq_mask = in i965_irq_postinstall()
4237 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
4239 /* Interrupt setup is already guaranteed to be single-threaded, this is in i965_irq_postinstall()
4241 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4245 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4254 lockdep_assert_held(&dev_priv->irq_lock); in i915_hpd_irq_setup()
4284 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
4292 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i965_irq_handler()
4308 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i965_irq_handler()
4311 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], in i965_irq_handler()
4315 intel_engine_cs_irq(dev_priv->gt.engine[VCS0], in i965_irq_handler()
4329 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
4335 * intel_irq_init - initializes irq support
4343 struct drm_device *dev = &dev_priv->drm; in intel_irq_init()
4346 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); in intel_irq_init()
4348 dev_priv->l3_parity.remap_info[i] = NULL; in intel_irq_init()
4350 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ in intel_irq_init()
4352 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; in intel_irq_init()
4361 dev->vblank_disable_immediate = true; in intel_irq_init()
4363 /* Most platforms treat the display irq block as an always-on in intel_irq_init()
4369 dev_priv->display_irqs_enabled = true; in intel_irq_init()
4371 dev_priv->display_irqs_enabled = false; in intel_irq_init()
4373 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; in intel_irq_init()
4380 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); in intel_irq_init()
4384 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4387 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; in intel_irq_init()
4389 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; in intel_irq_init()
4391 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; in intel_irq_init()
4393 dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup; in intel_irq_init()
4395 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; in intel_irq_init()
4397 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4402 * intel_irq_fini - deinitializes IRQ support
4412 kfree(i915->l3_parity.remap_info[i]); in intel_irq_fini()
4491 * intel_irq_install - enables the hardware interrupt
4499 * workers. Hence the split into this two-stage approach.
4503 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_install()
4511 dev_priv->runtime_pm.irqs_enabled = true; in intel_irq_install()
4513 dev_priv->irq_enabled = true; in intel_irq_install()
4520 dev_priv->irq_enabled = false; in intel_irq_install()
4530 * intel_irq_uninstall - finilizes all irq handling
4538 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_uninstall()
4546 if (!dev_priv->irq_enabled) in intel_irq_uninstall()
4549 dev_priv->irq_enabled = false; in intel_irq_uninstall()
4556 dev_priv->runtime_pm.irqs_enabled = false; in intel_irq_uninstall()
4560 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4569 dev_priv->runtime_pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4574 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4582 dev_priv->runtime_pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4589 return dev_priv->runtime_pm.irqs_enabled; in intel_irqs_enabled()
4594 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); in intel_synchronize_irq()
4599 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); in intel_synchronize_hardirq()