1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
38 #include <linux/io-mapping.h>
40 #include <linux/i2c-algo-bit.h>
43 #include <linux/intel-iommu.h>
48 #include <linux/dma-resv.h>
53 #include <drm/intel-gtt.h>
177 	 * if we get a HPD irq from DP and a HPD irq from non-DP
178 	 * the non-DP HPD could block the workqueue on a mode config
181 	 * blocked behind the non-DP one.
227 	 * until all current in-flight work is complete, swap in the new
238 	 * the proto-context can't handle.  Then the struct i915_gem_context
244 	 * it NULL, and place the proto-context in the corresponding slot
249 	 * context and kill the proto-context.
256 	 * fast-path anyway.
296  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
297  *      - Support vertical blank on secondary display pipe
350 	 * fills out the pipe-config with the hw state. */
398 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
466 	 * and re-enable FBC for a new configuration we just check if there's
640 	/* Non-NULL if port present. */
687 		int preemphasis;  member
771 	u8 level;  member
790 	return entry->end - entry->start;  in skl_ddb_entry_size()
796 	if (e1->start == e2->start && e1->end == e2->end)  in skl_ddb_entry_equal()
843 	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
964 	 * wq - Driver workqueue for GEM.
1069 	 * av_mutex - mutex for audio/video sync
1132 		 * protects * intel_crtc->wm.active and
1133 		 * crtc_state->wm.need_postvbl_update.
1208 	/* Used to save the pipe-to-encoder mapping for audio */
1256 		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1260 	for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1262 	     ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1269 	for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1271 	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1275 	     (engine__) && (engine__)->uabi_class == (class__); \
1276 	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1278 #define I915_GTT_OFFSET_NONE ((u32)-1)
1281  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1282  * considered to be the frontbuffer for the given plane interface-wise. This
1295 	BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1297 	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1300 #define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
1301 #define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
1302 #define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
1304 #define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
1308 #define GRAPHICS_VER(i915)		(INTEL_INFO(i915)->graphics_ver)
1309 #define GRAPHICS_VER_FULL(i915)		IP_VER(INTEL_INFO(i915)->graphics_ver, \
1310 					       INTEL_INFO(i915)->graphics_rel)
1314 #define MEDIA_VER(i915)			(INTEL_INFO(i915)->media_ver)
1315 #define MEDIA_VER_FULL(i915)		IP_VER(INTEL_INFO(i915)->media_ver, \
1316 					       INTEL_INFO(i915)->media_rel)
1320 #define DISPLAY_VER(i915)	(INTEL_INFO(i915)->display.ver)
1324 #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)
1326 #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
1328 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1329 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1332 	(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1336 	(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1344 		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;  in __platform_mask_index()
1348 		     pbits * ARRAY_SIZE(info->platform_mask));  in __platform_mask_index()
1358 		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;  in __platform_mask_bit()
1368 	return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;  in intel_subplatform()
1380 	return info->platform_mask[pi] & BIT(pb);  in IS_PLATFORM()
1390 	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;  in IS_SUBPLATFORM()
1391 	const u32 mask = info->platform_mask[pi];  in IS_SUBPLATFORM()
1398 	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);  in IS_SUBPLATFORM()
1401 #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
1402 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1425 				 INTEL_INFO(dev_priv)->gt == 1)
1458 				 INTEL_INFO(dev_priv)->gt == 3)
1462 				 INTEL_INFO(dev_priv)->gt == 3)
1464 				 INTEL_INFO(dev_priv)->gt == 1)
1477 				 INTEL_INFO(dev_priv)->gt == 2)
1479 				 INTEL_INFO(dev_priv)->gt == 3)
1481 				 INTEL_INFO(dev_priv)->gt == 4)
1483 				 INTEL_INFO(dev_priv)->gt == 2)
1485 				 INTEL_INFO(dev_priv)->gt == 3)
1491 				 INTEL_INFO(dev_priv)->gt == 2)
1493 				 INTEL_INFO(dev_priv)->gt == 3)
1500 				 INTEL_INFO(dev_priv)->gt == 2)
1568  * reset in the same manner --- a specific stepping like "B0" has a consistent
1571  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
1573  * and stepping-specific logic will be applied with a general DG2-wide stepping
1584 #define IS_LP(dev_priv)		(INTEL_INFO(dev_priv)->is_lp)
1589 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1594 	((gt)->info.engine_mask &						\
1595 	 GENMASK(first__ + count__ - 1, first__)) >> first__;		\
1608 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
1609 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
1610 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
1614 #define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
1617 		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1619 		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1623 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1631 	((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1634 #define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)
1636 		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1653 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1658 #define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
1659 #define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
1662 #define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_fbc)
1667 #define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
1669 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
1670 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
1671 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1672 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
1674 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1676 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) …
1678 #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
1679 #define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
1682 #define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
1684 #define HAS_DMC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dmc)
1688 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1689 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1692 	(INTEL_INFO(dev_priv)->has_mslices)
1694 #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
1696 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1699 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
1701 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
1703 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
1706 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1711 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1718 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1720 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1726 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1792 	while (atomic_read(&i915->mm.free_count)) {  in i915_gem_drain_freed_objects()
1793 		flush_work(&i915->mm.free_work);  in i915_gem_drain_freed_objects()
1801 	 * Similar to objects above (see i915_gem_drain_freed-objects), in  in i915_gem_drain_workqueue()
1813 		flush_workqueue(i915->wq);  in i915_gem_drain_workqueue()
1816 	} while (--pass);  in i915_gem_drain_workqueue()
1817 	drain_workqueue(i915->wq);  in i915_gem_drain_workqueue()
1851 	return atomic_read(&error->reset_count);  in i915_reset_count()
1857 	return atomic_read(&error->reset_engine_count[engine->uabi_class]);  in i915_reset_engine_count()
1885 	vm = xa_load(&file_priv->vm_xa, id);  in i915_gem_vm_lookup()
1886 	if (vm && !kref_get_unless_zero(&vm->ref))  in i915_gem_vm_lookup()
1912 	struct drm_i915_private *i915 = to_i915(obj->base.dev);  in i915_gem_object_needs_bit17_swizzle()
1914 	return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&  in i915_gem_object_needs_bit17_swizzle()