47 	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
48 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
49 	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
50 	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
51 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
52 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
53 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
54 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
55 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
56 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
57 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
58 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
59 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
60 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
61 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
62 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
63 	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
64 	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
65 	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
66 	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
67 	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
68 	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
70 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
71 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
72 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
73 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
74 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
75 	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
79 	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
80 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
81 	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
82 	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
83 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
84 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
85 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
86 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
87 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
88 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
89 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
90 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
91 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
92 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
93 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
94 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
95 	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
96 	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
97 	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
98 	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
99 	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
100 	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
102 	{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
103 	{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
104 	{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
105 	{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
106 	{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
107 	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
108 	{RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */
109 	{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
110 	{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
111 	{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
112 	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
113 	{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
114 	{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
115 	{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
116 	{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
117 	{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
118 	{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
119 	{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
120 	{RCS0, TRVADR, 0, true}, /* 0x4df0 */
121 	{RCS0, TRTTE, 0, true}, /* 0x4df4 */
122 	{RCS0, _MMIO(0x4dfc), 0, true},
124 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
125 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
126 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
127 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
128 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
130 	{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
132 	{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
134 	{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
135 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
136 	{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
137 	{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
139 	{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
140 	{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
141 	{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
143 	{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
144 	{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
145 	{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
146 	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
156 	[RCS0]  = 0xc800,
157 	[VCS0]  = 0xc900,
158 	[VCS1]  = 0xca00,
159 	[BCS0]  = 0xcc00,
160 	[VECS0] = 0xcb00,
176 	for (ring_id = 0; ring_id < cnt; ring_id++) {  in load_render_mocs()
181 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {  in load_render_mocs()
188 	offset.reg = 0xb020;  in load_render_mocs()
189 	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {  in load_render_mocs()
208 	if (count == 0)  in restore_context_mmio_for_inhibit()
209 		return 0;  in restore_context_mmio_for_inhibit()
227 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",  in restore_context_mmio_for_inhibit()
238 	return 0;  in restore_context_mmio_for_inhibit()
254 	for (index = 0; index < GEN9_MOCS_SIZE; index++) {  in restore_render_mocs_control_for_inhibit()
257 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",  in restore_render_mocs_control_for_inhibit()
265 	return 0;  in restore_render_mocs_control_for_inhibit()
281 	for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {  in restore_render_mocs_l3cc_for_inhibit()
284 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",  in restore_render_mocs_l3cc_for_inhibit()
292 	return 0;  in restore_render_mocs_l3cc_for_inhibit()
343 	[RCS0]  = 0x4260,
344 	[VCS0]  = 0x4264,
345 	[VCS1]  = 0x4268,
346 	[BCS0]  = 0x426c,
347 	[VECS0] = 0x4270,
383 	intel_uncore_write_fw(uncore, reg, 0x1);  in handle_tlb_pending_event()
385 	if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50))  in handle_tlb_pending_event()
389 		vgpu_vreg_t(vgpu, reg) = 0;  in handle_tlb_pending_event()
400 		[RCS0]  = 0xc800,  in switch_mocs()
401 		[VCS0]  = 0xc900,  in switch_mocs()
402 		[VCS1]  = 0xca00,  in switch_mocs()
403 		[BCS0]  = 0xcc00,  in switch_mocs()
404 		[VECS0] = 0xcb00,  in switch_mocs()
421 	for (i = 0; i < GEN9_MOCS_SIZE; i++) {  in switch_mocs()
438 		l3_offset.reg = 0xb020;  in switch_mocs()
439 		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {  in switch_mocs()
457 #define CTX_CONTEXT_CONTROL_VAL	0x03
535 		trace_render_mmio(pre ? pre->id : 0,  in switch_mmio()
536 				  next ? next->id : 0,  in switch_mmio()