33 	} engine[I915_NUM_ENGINES];  member
63 	struct intel_engine_cs *engine;  in reference_lists_init()  local
72 	for_each_engine(engine, gt, id) {  in reference_lists_init()
73 		struct i915_wa_list *wal = &lists->engine[id].wa_list;  in reference_lists_init()
75 		wa_init_start(wal, "REF", engine->name);  in reference_lists_init()
76 		engine_init_workarounds(engine, wal);  in reference_lists_init()
79 		__intel_engine_init_ctx_wa(engine,  in reference_lists_init()
80 					   &lists->engine[id].ctx_wa_list,  in reference_lists_init()
88 	struct intel_engine_cs *engine;  in reference_lists_fini()  local
91 	for_each_engine(engine, gt, id)  in reference_lists_fini()
92 		intel_wa_list_free(&lists->engine[id].wa_list);  in reference_lists_fini()
100 	struct intel_engine_cs *engine = ce->engine;  in read_nonprivs()  local
101 	const u32 base = engine->mmio_base;  in read_nonprivs()
109 	result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);  in read_nonprivs()
124 	vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);  in read_nonprivs()
149 	if (GRAPHICS_VER(engine->i915) >= 8)  in read_nonprivs()
181 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)  in get_whitelist_reg()  argument
183 	i915_reg_t reg = i < engine->whitelist.count ?  in get_whitelist_reg()
184 			 engine->whitelist.list[i].reg :  in get_whitelist_reg()
185 			 RING_NOPID(engine->mmio_base);  in get_whitelist_reg()
191 print_results(const struct intel_engine_cs *engine, const u32 *results)  in print_results()  argument
196 		u32 expected = get_whitelist_reg(engine, i);  in print_results()
206 	struct intel_engine_cs *engine = ce->engine;  in check_whitelist()  local
219 	intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */  in check_whitelist()
222 	if (intel_gt_is_wedged(engine->gt))  in check_whitelist()
234 		u32 expected = get_whitelist_reg(engine, i);  in check_whitelist()
238 			print_results(engine, vaddr);  in check_whitelist()
254 static int do_device_reset(struct intel_engine_cs *engine)  in do_device_reset()  argument
256 	intel_gt_reset(engine->gt, engine->mask, "live_workarounds");  in do_device_reset()
260 static int do_engine_reset(struct intel_engine_cs *engine)  in do_engine_reset()  argument
262 	return intel_engine_reset(engine, "live_workarounds");  in do_engine_reset()
265 static int do_guc_reset(struct intel_engine_cs *engine)  in do_guc_reset()  argument
272 switch_to_scratch_context(struct intel_engine_cs *engine,  in switch_to_scratch_context()  argument
279 	ce = intel_context_create(engine);  in switch_to_scratch_context()
300 static int check_whitelist_across_reset(struct intel_engine_cs *engine,  in check_whitelist_across_reset()  argument
311 		engine->whitelist.count, engine->name, name);  in check_whitelist_across_reset()
313 	ce = intel_context_create(engine);  in check_whitelist_across_reset()
317 	err = igt_spinner_init(&spin, engine->gt);  in check_whitelist_across_reset()
327 	err = switch_to_scratch_context(engine, &spin, &rq);  in check_whitelist_across_reset()
338 	with_intel_runtime_pm(engine->uncore->rpm, wakeref)  in check_whitelist_across_reset()
339 		err = reset(engine);  in check_whitelist_across_reset()
341 	/* Ensure the reset happens and kills the engine */  in check_whitelist_across_reset()
359 	tmp = intel_context_create(engine);  in check_whitelist_across_reset()
421 static bool wo_register(struct intel_engine_cs *engine, u32 reg)  in wo_register()  argument
423 	enum intel_platform platform = INTEL_INFO(engine->i915)->platform;  in wo_register()
439 static bool timestamp(const struct intel_engine_cs *engine, u32 reg)  in timestamp()  argument
441 	reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;  in timestamp()
462 static int whitelist_writable_count(struct intel_engine_cs *engine)  in whitelist_writable_count()  argument
464 	int count = engine->whitelist.count;  in whitelist_writable_count()
467 	for (i = 0; i < engine->whitelist.count; i++) {  in whitelist_writable_count()
468 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);  in whitelist_writable_count()
505 	struct intel_engine_cs *engine = ce->engine;  in check_dirty_whitelist()  local
522 	for (i = 0; i < engine->whitelist.count; i++) {  in check_dirty_whitelist()
523 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);  in check_dirty_whitelist()
532 		if (wo_register(engine, reg))  in check_dirty_whitelist()
535 		if (timestamp(engine, reg))  in check_dirty_whitelist()
568 		if (GRAPHICS_VER(engine->i915) >= 8)  in check_dirty_whitelist()
572 			 engine->name, reg);  in check_dirty_whitelist()
619 		intel_gt_chipset_flush(engine->gt);  in check_dirty_whitelist()
628 		if (engine->emit_init_breadcrumb) { /* Be nice if we hang */  in check_dirty_whitelist()
629 			err = engine->emit_init_breadcrumb(rq);  in check_dirty_whitelist()
647 		err = engine->emit_bb_start(rq,  in check_dirty_whitelist()
657 			       engine->name, reg);  in check_dirty_whitelist()
658 			intel_gt_set_wedged(engine->gt);  in check_dirty_whitelist()
668 				       engine->name, reg);  in check_dirty_whitelist()
700 			       engine->name, err, reg);  in check_dirty_whitelist()
704 					engine->name, reg, results[0]);  in check_dirty_whitelist()
707 					engine->name, reg, results[0], rsvd);  in check_dirty_whitelist()
754 	if (igt_flush_test(engine->i915))  in check_dirty_whitelist()
766 	struct intel_engine_cs *engine;  in live_dirty_whitelist()  local
774 	for_each_engine(engine, gt, id) {  in live_dirty_whitelist()
778 		if (engine->whitelist.count == 0)  in live_dirty_whitelist()
781 		ce = intel_context_create(engine);  in live_dirty_whitelist()
797 	struct intel_engine_cs *engine;  in live_reset_whitelist()  local
804 	for_each_engine(engine, gt, id) {  in live_reset_whitelist()
805 		if (engine->whitelist.count == 0)  in live_reset_whitelist()
809 			if (intel_engine_uses_guc(engine)) {  in live_reset_whitelist()
813 				err = intel_selftest_modify_policy(engine, &saved,  in live_reset_whitelist()
818 				err = check_whitelist_across_reset(engine,  in live_reset_whitelist()
822 				err2 = intel_selftest_restore_policy(engine, &saved);  in live_reset_whitelist()
826 				err = check_whitelist_across_reset(engine,  in live_reset_whitelist()
828 								   "engine");  in live_reset_whitelist()
836 			err = check_whitelist_across_reset(engine,  in live_reset_whitelist()
852 	struct intel_engine_cs *engine = ce->engine;  in read_whitelisted_registers()  local
870 	if (GRAPHICS_VER(engine->i915) >= 8)  in read_whitelisted_registers()
873 	cs = intel_ring_begin(rq, 4 * engine->whitelist.count);  in read_whitelisted_registers()
879 	for (i = 0; i < engine->whitelist.count; i++) {  in read_whitelisted_registers()
881 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);  in read_whitelisted_registers()
899 	struct intel_engine_cs *engine = ce->engine;  in scrub_whitelisted_registers()  local
915 	*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));  in scrub_whitelisted_registers()
916 	for (i = 0; i < engine->whitelist.count; i++) {  in scrub_whitelisted_registers()
917 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);  in scrub_whitelisted_registers()
931 	intel_gt_chipset_flush(engine->gt);  in scrub_whitelisted_registers()
939 	if (engine->emit_init_breadcrumb) { /* Be nice if we hang */  in scrub_whitelisted_registers()
940 		err = engine->emit_init_breadcrumb(rq);  in scrub_whitelisted_registers()
954 	err = engine->emit_bb_start(rq, batch->node.start, 0, 0);  in scrub_whitelisted_registers()
999 static bool result_eq(struct intel_engine_cs *engine,  in result_eq()  argument
1002 	if (a != b && !pardon_reg(engine->i915, reg)) {  in result_eq()
1021 static bool result_neq(struct intel_engine_cs *engine,  in result_neq()  argument
1024 	if (a == b && !writeonly_reg(engine->i915, reg)) {  in result_neq()
1034 check_whitelisted_registers(struct intel_engine_cs *engine,  in check_whitelisted_registers()  argument
1037 			    bool (*fn)(struct intel_engine_cs *engine,  in check_whitelisted_registers()  argument
1055 	for (i = 0; i < engine->whitelist.count; i++) {  in check_whitelisted_registers()
1056 		const struct i915_wa *wa = &engine->whitelist.list[i];  in check_whitelisted_registers()
1062 		if (!fn(engine, a[i], b[i], wa->reg))  in check_whitelisted_registers()
1078 	struct intel_engine_cs *engine;  in live_isolated_whitelist()  local
1107 	for_each_engine(engine, gt, id) {  in live_isolated_whitelist()
1110 		if (!engine->kernel_context->vm)  in live_isolated_whitelist()
1113 		if (!whitelist_writable_count(engine))  in live_isolated_whitelist()
1116 		ce[0] = intel_context_create(engine);  in live_isolated_whitelist()
1121 		ce[1] = intel_context_create(engine);  in live_isolated_whitelist()
1144 		err = check_whitelisted_registers(engine,  in live_isolated_whitelist()
1157 		err = check_whitelisted_registers(engine,  in live_isolated_whitelist()
1184 	struct intel_engine_cs *engine;  in verify_wa_lists()  local
1190 	for_each_engine(engine, gt, id) {  in verify_wa_lists()
1193 		ce = intel_context_create(engine);  in verify_wa_lists()
1198 					    &lists->engine[id].wa_list,  in verify_wa_lists()
1202 					    &lists->engine[id].ctx_wa_list,  in verify_wa_lists()
1254 	struct intel_engine_cs *engine;  in live_engine_reset_workarounds()  local
1275 	for_each_engine(engine, gt, id) {  in live_engine_reset_workarounds()
1277 		bool using_guc = intel_engine_uses_guc(engine);  in live_engine_reset_workarounds()
1281 		pr_info("Verifying after %s reset...\n", engine->name);  in live_engine_reset_workarounds()
1282 		ret = intel_selftest_modify_policy(engine, &saved,  in live_engine_reset_workarounds()
1287 		ce = intel_context_create(engine);  in live_engine_reset_workarounds()
1300 			ret = intel_engine_reset(engine, "live_workarounds:idle");  in live_engine_reset_workarounds()
1302 				pr_err("%s: Reset failed while idle\n", engine->name);  in live_engine_reset_workarounds()
1313 		ret = igt_spinner_init(&spin, engine->gt);  in live_engine_reset_workarounds()
1326 			pr_err("%s: Spinner failed to start\n", engine->name);  in live_engine_reset_workarounds()
1338 			ret = intel_engine_reset(engine, "live_workarounds:active");  in live_engine_reset_workarounds()
1341 				       engine->name);  in live_engine_reset_workarounds()
1347 		/* Ensure the reset happens and kills the engine */  in live_engine_reset_workarounds()
1363 		ret2 = intel_selftest_restore_policy(engine, &saved);  in live_engine_reset_workarounds()