28 	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)  in intel_sseu_subslice_total()
29 		total += hweight8(sseu->subslice_mask[i]);  in intel_sseu_subslice_total()
42 		mask |= (u32)sseu->subslice_mask[offset + i] <<  in intel_sseu_get_subslices()
53 	memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride);  in intel_sseu_set_subslices()
214 	u8 subslice_mask = 0;  in cherryview_sseu_info_init()  local
228 		subslice_mask |= BIT(0);  in cherryview_sseu_info_init()
239 		subslice_mask |= BIT(1);  in cherryview_sseu_info_init()
243 	intel_sseu_set_subslices(sseu, 0, subslice_mask);  in cherryview_sseu_info_init()
271 	u32 fuse2, eu_disable, subslice_mask;  in gen9_sseu_info_init()  local
286 	subslice_mask = (1 << sseu->max_subslices) - 1;  in gen9_sseu_info_init()
287 	subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>  in gen9_sseu_info_init()
299 		intel_sseu_set_subslices(sseu, s, subslice_mask);  in gen9_sseu_info_init()
356 #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask[0] & BIT(ss)))  in gen9_sseu_info_init()
357 		info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;  in gen9_sseu_info_init()
377 	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */  in bdw_sseu_info_init()  local
388 	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);  in bdw_sseu_info_init()
389 	subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>  in bdw_sseu_info_init()
411 		intel_sseu_set_subslices(sseu, s, subslice_mask);  in bdw_sseu_info_init()
462 	u8 subslice_mask = 0;  in hsw_sseu_info_init()  local
475 		subslice_mask = BIT(0);  in hsw_sseu_info_init()
479 		subslice_mask = BIT(0) | BIT(1);  in hsw_sseu_info_init()
483 		subslice_mask = BIT(0) | BIT(1);  in hsw_sseu_info_init()
505 			    hweight8(subslice_mask),  in hsw_sseu_info_init()
509 		intel_sseu_set_subslices(sseu, s, subslice_mask);  in hsw_sseu_info_init()
567 	subslices = hweight8(req_sseu->subslice_mask);  in intel_sseu_make_rpcs()
596 	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {  in intel_sseu_make_rpcs()