34 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)  in intel_sseu_get_subslices()  argument
36 	int i, offset = slice * sseu->ss_stride;  in intel_sseu_get_subslices()
39 	GEM_BUG_ON(slice >= sseu->max_slices);  in intel_sseu_get_subslices()
48 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,  in intel_sseu_set_subslices()  argument
51 	int offset = slice * sseu->ss_stride;  in intel_sseu_set_subslices()
57 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)  in intel_sseu_subslices_per_slice()  argument
59 	return hweight32(intel_sseu_get_subslices(sseu, slice));  in intel_sseu_subslices_per_slice()
62 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,  in sseu_eu_idx()  argument
67 	return slice * slice_stride + subslice * sseu->eu_stride;  in sseu_eu_idx()
70 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,  in sseu_get_eus()  argument
73 	int i, offset = sseu_eu_idx(sseu, slice, subslice);  in sseu_get_eus()
83 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,  in sseu_set_eus()  argument
86 	int i, offset = sseu_eu_idx(sseu, slice, subslice);  in sseu_set_eus()
143 	 * In addition, the concept of slice has been removed in Xe_HP.  in gen12_sseu_info_init()
144 	 * To be compatible with prior generations, assume a single slice  in gen12_sseu_info_init()
146 	 * workload type within that software slice.  in gen12_sseu_info_init()
154 	 * As mentioned above, Xe_HP does not have the concept of a slice.  in gen12_sseu_info_init()
178 	/* TGL only supports slice-level power gating */  in gen12_sseu_info_init()
278 	/* BXT has a single slice and at most 3 subslices. */  in gen9_sseu_info_init()
296 			/* skip disabled slice */  in gen9_sseu_info_init()
342 	 * SKL+ supports slice power gating on devices with more than  in gen9_sseu_info_init()
343 	 * one slice, and supports EU power gating on devices with  in gen9_sseu_info_init()
408 			/* skip disabled slice */  in bdw_sseu_info_init()
449 	 * BDW supports slice power gating on devices with more than  in bdw_sseu_info_init()
450 	 * one slice.  in bdw_sseu_info_init()
554 	 * slice/subslice/EU enablement prior to Gen9.  in intel_sseu_make_rpcs()
585 	 * When more than one slice is enabled, hardware ignores the subslice  in intel_sseu_make_rpcs()
592 	 * slice.  in intel_sseu_make_rpcs()
605 	 * slice/subslice/EU in a partially enabled state. We  in intel_sseu_make_rpcs()
662 	drm_printf(p, "slice total: %u, mask=%04x\n",  in intel_sseu_dump()
666 		drm_printf(p, "slice%d: %u subslices, mask=%08x\n",  in intel_sseu_dump()
672 	drm_printf(p, "has slice power gating: %s\n",  in intel_sseu_dump()
690 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",  in intel_sseu_print_topology()