26 static void set_hwstam(struct intel_engine_cs *engine, u32 mask)  in set_hwstam()  argument
32 	if (engine->class == RENDER_CLASS) {  in set_hwstam()
33 		if (GRAPHICS_VER(engine->i915) >= 6)  in set_hwstam()
39 	intel_engine_set_hwsp_writemask(engine, mask);  in set_hwstam()
42 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)  in set_hws_pga()  argument
47 	if (GRAPHICS_VER(engine->i915) >= 4)  in set_hws_pga()
50 	intel_uncore_write(engine->uncore, HWS_PGA, addr);  in set_hws_pga()
53 static struct page *status_page(struct intel_engine_cs *engine)  in status_page()  argument
55 	struct drm_i915_gem_object *obj = engine->status_page.vma->obj;  in status_page()
61 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)  in ring_setup_phys_status_page()  argument
63 	set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));  in ring_setup_phys_status_page()
64 	set_hwstam(engine, ~0u);  in ring_setup_phys_status_page()
67 static void set_hwsp(struct intel_engine_cs *engine, u32 offset)  in set_hwsp()  argument
75 	if (GRAPHICS_VER(engine->i915) == 7) {  in set_hwsp()
76 		switch (engine->id) {  in set_hwsp()
82 			GEM_BUG_ON(engine->id);  in set_hwsp()
97 	} else if (GRAPHICS_VER(engine->i915) == 6) {  in set_hwsp()
98 		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);  in set_hwsp()
100 		hwsp = RING_HWS_PGA(engine->mmio_base);  in set_hwsp()
103 	intel_uncore_write_fw(engine->uncore, hwsp, offset);  in set_hwsp()
104 	intel_uncore_posting_read_fw(engine->uncore, hwsp);  in set_hwsp()
107 static void flush_cs_tlb(struct intel_engine_cs *engine)  in flush_cs_tlb()  argument
109 	if (!IS_GRAPHICS_VER(engine->i915, 6, 7))  in flush_cs_tlb()
113 	GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);  in flush_cs_tlb()
115 	ENGINE_WRITE_FW(engine, RING_INSTPM,  in flush_cs_tlb()
118 	if (__intel_wait_for_register_fw(engine->uncore,  in flush_cs_tlb()
119 					 RING_INSTPM(engine->mmio_base),  in flush_cs_tlb()
122 		ENGINE_TRACE(engine,  in flush_cs_tlb()
126 static void ring_setup_status_page(struct intel_engine_cs *engine)  in ring_setup_status_page()  argument
128 	set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));  in ring_setup_status_page()
129 	set_hwstam(engine, ~0u);  in ring_setup_status_page()
131 	flush_cs_tlb(engine);  in ring_setup_status_page()
147 static void set_pp_dir(struct intel_engine_cs *engine)  in set_pp_dir()  argument
149 	struct i915_address_space *vm = vm_alias(engine->gt->vm);  in set_pp_dir()
154 	ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);  in set_pp_dir()
155 	ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));  in set_pp_dir()
157 	if (GRAPHICS_VER(engine->i915) >= 7) {  in set_pp_dir()
158 		ENGINE_WRITE_FW(engine,  in set_pp_dir()
164 static bool stop_ring(struct intel_engine_cs *engine)  in stop_ring()  argument
167 	ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));  in stop_ring()
168 	ENGINE_POSTING_READ(engine, RING_HEAD);  in stop_ring()
171 	ENGINE_WRITE_FW(engine, RING_CTL, 0);  in stop_ring()
172 	ENGINE_POSTING_READ(engine, RING_CTL);  in stop_ring()
175 	ENGINE_WRITE_FW(engine, RING_HEAD, 0);  in stop_ring()
176 	ENGINE_WRITE_FW(engine, RING_TAIL, 0);  in stop_ring()
178 	return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;  in stop_ring()
181 static int xcs_resume(struct intel_engine_cs *engine)  in xcs_resume()  argument
183 	struct intel_ring *ring = engine->legacy.ring;  in xcs_resume()
185 	ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",  in xcs_resume()
192 	intel_synchronize_hardirq(engine->i915);  in xcs_resume()
193 	if (!stop_ring(engine))  in xcs_resume()
196 	if (HWS_NEEDS_PHYSICAL(engine->i915))  in xcs_resume()
197 		ring_setup_phys_status_page(engine);  in xcs_resume()
199 		ring_setup_status_page(engine);  in xcs_resume()
201 	intel_breadcrumbs_reset(engine->breadcrumbs);  in xcs_resume()
204 	ENGINE_POSTING_READ(engine, RING_HEAD);  in xcs_resume()
212 	ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));  in xcs_resume()
219 	set_pp_dir(engine);  in xcs_resume()
222 	ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);  in xcs_resume()
223 	ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);  in xcs_resume()
224 	ENGINE_POSTING_READ(engine, RING_TAIL);  in xcs_resume()
226 	ENGINE_WRITE_FW(engine, RING_CTL,  in xcs_resume()
230 	if (__intel_wait_for_register_fw(engine->uncore,  in xcs_resume()
231 					 RING_CTL(engine->mmio_base),  in xcs_resume()
236 	if (GRAPHICS_VER(engine->i915) > 2)  in xcs_resume()
237 		ENGINE_WRITE_FW(engine,  in xcs_resume()
242 		ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);  in xcs_resume()
243 		ENGINE_POSTING_READ(engine, RING_TAIL);  in xcs_resume()
247 	intel_engine_signal_breadcrumbs(engine);  in xcs_resume()
251 	drm_err(&engine->i915->drm,  in xcs_resume()
254 		engine->name,  in xcs_resume()
255 		ENGINE_READ(engine, RING_CTL),  in xcs_resume()
256 		ENGINE_READ(engine, RING_CTL) & RING_VALID,  in xcs_resume()
257 		ENGINE_READ(engine, RING_HEAD), ring->head,  in xcs_resume()
258 		ENGINE_READ(engine, RING_TAIL), ring->tail,  in xcs_resume()
259 		ENGINE_READ(engine, RING_START),  in xcs_resume()
264 static void sanitize_hwsp(struct intel_engine_cs *engine)  in sanitize_hwsp()  argument
268 	list_for_each_entry(tl, &engine->status_page.timelines, engine_link)  in sanitize_hwsp()
272 static void xcs_sanitize(struct intel_engine_cs *engine)  in xcs_sanitize()  argument
284 		memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);  in xcs_sanitize()
291 	sanitize_hwsp(engine);  in xcs_sanitize()
294 	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);  in xcs_sanitize()
297 static void reset_prepare(struct intel_engine_cs *engine)  in reset_prepare()  argument
314 	ENGINE_TRACE(engine, "\n");  in reset_prepare()
315 	intel_engine_stop_cs(engine);  in reset_prepare()
317 	if (!stop_ring(engine)) {  in reset_prepare()
319 		ENGINE_TRACE(engine,  in reset_prepare()
322 			     ENGINE_READ_FW(engine, RING_CTL),  in reset_prepare()
323 			     ENGINE_READ_FW(engine, RING_HEAD),  in reset_prepare()
324 			     ENGINE_READ_FW(engine, RING_TAIL),  in reset_prepare()
325 			     ENGINE_READ_FW(engine, RING_START));  in reset_prepare()
326 		if (!stop_ring(engine)) {  in reset_prepare()
327 			drm_err(&engine->i915->drm,  in reset_prepare()
330 				engine->name,  in reset_prepare()
331 				ENGINE_READ_FW(engine, RING_CTL),  in reset_prepare()
332 				ENGINE_READ_FW(engine, RING_HEAD),  in reset_prepare()
333 				ENGINE_READ_FW(engine, RING_TAIL),  in reset_prepare()
334 				ENGINE_READ_FW(engine, RING_START));  in reset_prepare()
339 static void reset_rewind(struct intel_engine_cs *engine, bool stalled)  in reset_rewind()  argument
346 	spin_lock_irqsave(&engine->sched_engine->lock, flags);  in reset_rewind()
348 	list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) {  in reset_rewind()
357 	 * The guilty request will get skipped on a hung engine.  in reset_rewind()
396 		GEM_BUG_ON(rq->ring != engine->legacy.ring);  in reset_rewind()
399 		head = engine->legacy.ring->tail;  in reset_rewind()
401 	engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);  in reset_rewind()
403 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);  in reset_rewind()
406 static void reset_finish(struct intel_engine_cs *engine)  in reset_finish()  argument
410 static void reset_cancel(struct intel_engine_cs *engine)  in reset_cancel()  argument
415 	spin_lock_irqsave(&engine->sched_engine->lock, flags);  in reset_cancel()
418 	list_for_each_entry(request, &engine->sched_engine->requests, sched.link)  in reset_cancel()
420 	intel_engine_signal_breadcrumbs(engine);  in reset_cancel()
424 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);  in reset_cancel()
432 	ENGINE_WRITE(request->engine, RING_TAIL,  in i9xx_submit_request()
464 	shmem_read(ce->engine->default_state, 0,  in ring_context_init_default_state()
465 		   vaddr, ce->engine->context_size);  in ring_context_init_default_state()
481 	if (ce->engine->default_state &&  in ring_context_pre_pin()
514 alloc_context_vma(struct intel_engine_cs *engine)  in alloc_context_vma()  argument
516 	struct drm_i915_private *i915 = engine->i915;  in alloc_context_vma()
521 	obj = i915_gem_object_create_shmem(i915, engine->context_size);  in alloc_context_vma()
543 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);  in alloc_context_vma()
558 	struct intel_engine_cs *engine = ce->engine;  in ring_context_alloc()  local
561 	GEM_BUG_ON(!engine->legacy.ring);  in ring_context_alloc()
562 	ce->ring = engine->legacy.ring;  in ring_context_alloc()
563 	ce->timeline = intel_timeline_get(engine->legacy.timeline);  in ring_context_alloc()
566 	if (engine->context_size) {  in ring_context_alloc()
569 		vma = alloc_context_vma(engine);  in ring_context_alloc()
593 	struct intel_engine_cs *engine;  in ring_context_ban()  local
598 	engine = rq->engine;  in ring_context_ban()
599 	lockdep_assert_held(&engine->sched_engine->lock);  in ring_context_ban()
600 	list_for_each_entry_continue(rq, &engine->sched_engine->requests,  in ring_context_ban()
611 	struct intel_engine_cs *engine = NULL;  in ring_context_cancel_request()  local
613 	i915_request_active_engine(rq, &engine);  in ring_context_cancel_request()
615 	if (engine && intel_engine_pulse(engine))  in ring_context_cancel_request()
616 		intel_gt_handle_error(engine->gt, engine->mask, 0,  in ring_context_cancel_request()
644 	const struct intel_engine_cs * const engine = rq->engine;  in load_pd_dir()  local
652 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));  in load_pd_dir()
656 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));  in load_pd_dir()
661 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));  in load_pd_dir()
662 	*cs++ = intel_gt_scratch_offset(engine->gt,  in load_pd_dir()
666 	*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));  in load_pd_dir()
671 	return rq->engine->emit_flush(rq, EMIT_FLUSH);  in load_pd_dir()
678 	struct intel_engine_cs *engine = rq->engine;  in mi_set_context()  local
679 	struct drm_i915_private *i915 = engine->i915;  in mi_set_context()
682 		IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;  in mi_set_context()
710 			for_each_engine(signaller, engine->gt, id) {  in mi_set_context()
711 				if (signaller == engine)  in mi_set_context()
744 		*cs++ = i915_ggtt_offset(engine->kernel_context->state) |  in mi_set_context()
764 			for_each_engine(signaller, engine->gt, id) {  in mi_set_context()
765 				if (signaller == engine)  in mi_set_context()
777 			*cs++ = intel_gt_scratch_offset(engine->gt,  in mi_set_context()
794 	u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];  in remap_l3_slice()
849 	ret = rq->engine->emit_flush(rq, EMIT_FLUSH);  in switch_mm()
865 	return rq->engine->emit_flush(rq, EMIT_INVALIDATE);  in switch_mm()
870 	struct intel_engine_cs *engine = rq->engine;  in clear_residuals()  local
873 	ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));  in clear_residuals()
877 	if (engine->kernel_context->state) {  in clear_residuals()
879 				     engine->kernel_context,  in clear_residuals()
885 	ret = engine->emit_bb_start(rq,  in clear_residuals()
886 				    engine->wa_ctx.vma->node.start, 0,  in clear_residuals()
891 	ret = engine->emit_flush(rq, EMIT_FLUSH);  in clear_residuals()
896 	return engine->emit_flush(rq, EMIT_INVALIDATE);  in clear_residuals()
901 	struct intel_engine_cs *engine = rq->engine;  in switch_context()  local
906 	GEM_BUG_ON(HAS_EXECLISTS(engine->i915));  in switch_context()
908 	if (engine->wa_ctx.vma && ce != engine->kernel_context) {  in switch_context()
909 		if (engine->wa_ctx.vma->private != ce &&  in switch_context()
915 			residuals = &engine->wa_ctx.vma->private;  in switch_context()
926 		GEM_BUG_ON(engine->id != RCS0);  in switch_context()
979 	ret = request->engine->emit_flush(request, EMIT_INVALIDATE);  in ring_request_alloc()
993 	struct intel_uncore *uncore = request->engine->uncore;  in gen6_bsd_submit_request()
1029 static void i9xx_set_default_submission(struct intel_engine_cs *engine)  in i9xx_set_default_submission()  argument
1031 	engine->submit_request = i9xx_submit_request;  in i9xx_set_default_submission()
1034 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)  in gen6_bsd_set_default_submission()  argument
1036 	engine->submit_request = gen6_bsd_submit_request;  in gen6_bsd_set_default_submission()
1039 static void ring_release(struct intel_engine_cs *engine)  in ring_release()  argument
1041 	struct drm_i915_private *dev_priv = engine->i915;  in ring_release()
1044 		    (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);  in ring_release()
1046 	intel_engine_cleanup_common(engine);  in ring_release()
1048 	if (engine->wa_ctx.vma) {  in ring_release()
1049 		intel_context_put(engine->wa_ctx.vma->private);  in ring_release()
1050 		i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);  in ring_release()
1053 	intel_ring_unpin(engine->legacy.ring);  in ring_release()
1054 	intel_ring_put(engine->legacy.ring);  in ring_release()
1056 	intel_timeline_unpin(engine->legacy.timeline);  in ring_release()
1057 	intel_timeline_put(engine->legacy.timeline);  in ring_release()
1060 static void irq_handler(struct intel_engine_cs *engine, u16 iir)  in irq_handler()  argument
1062 	intel_engine_signal_breadcrumbs(engine);  in irq_handler()
1065 static void setup_irq(struct intel_engine_cs *engine)  in setup_irq()  argument
1067 	struct drm_i915_private *i915 = engine->i915;  in setup_irq()
1069 	intel_engine_set_irq_handler(engine, irq_handler);  in setup_irq()
1072 		engine->irq_enable = gen6_irq_enable;  in setup_irq()
1073 		engine->irq_disable = gen6_irq_disable;  in setup_irq()
1075 		engine->irq_enable = gen5_irq_enable;  in setup_irq()
1076 		engine->irq_disable = gen5_irq_disable;  in setup_irq()
1078 		engine->irq_enable = gen3_irq_enable;  in setup_irq()
1079 		engine->irq_disable = gen3_irq_disable;  in setup_irq()
1081 		engine->irq_enable = gen2_irq_enable;  in setup_irq()
1082 		engine->irq_disable = gen2_irq_disable;  in setup_irq()
1088 	lockdep_assert_held(&rq->engine->sched_engine->lock);  in add_to_engine()
1089 	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);  in add_to_engine()
1094 	spin_lock_irq(&rq->engine->sched_engine->lock);  in remove_from_engine()
1100 	spin_unlock_irq(&rq->engine->sched_engine->lock);  in remove_from_engine()
1105 static void setup_common(struct intel_engine_cs *engine)  in setup_common()  argument
1107 	struct drm_i915_private *i915 = engine->i915;  in setup_common()
1112 	setup_irq(engine);  in setup_common()
1114 	engine->resume = xcs_resume;  in setup_common()
1115 	engine->sanitize = xcs_sanitize;  in setup_common()
1117 	engine->reset.prepare = reset_prepare;  in setup_common()
1118 	engine->reset.rewind = reset_rewind;  in setup_common()
1119 	engine->reset.cancel = reset_cancel;  in setup_common()
1120 	engine->reset.finish = reset_finish;  in setup_common()
1122 	engine->add_active_request = add_to_engine;  in setup_common()
1123 	engine->remove_active_request = remove_from_engine;  in setup_common()
1125 	engine->cops = &ring_context_ops;  in setup_common()
1126 	engine->request_alloc = ring_request_alloc;  in setup_common()
1131 	 * engine->emit_init_breadcrumb().  in setup_common()
1133 	engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;  in setup_common()
1135 		engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;  in setup_common()
1137 	engine->set_default_submission = i9xx_set_default_submission;  in setup_common()
1140 		engine->emit_bb_start = gen6_emit_bb_start;  in setup_common()
1142 		engine->emit_bb_start = gen4_emit_bb_start;  in setup_common()
1144 		engine->emit_bb_start = i830_emit_bb_start;  in setup_common()
1146 		engine->emit_bb_start = gen3_emit_bb_start;  in setup_common()
1149 static void setup_rcs(struct intel_engine_cs *engine)  in setup_rcs()  argument
1151 	struct drm_i915_private *i915 = engine->i915;  in setup_rcs()
1154 		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;  in setup_rcs()
1156 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;  in setup_rcs()
1159 		engine->emit_flush = gen7_emit_flush_rcs;  in setup_rcs()
1160 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;  in setup_rcs()
1162 		engine->emit_flush = gen6_emit_flush_rcs;  in setup_rcs()
1163 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;  in setup_rcs()
1165 		engine->emit_flush = gen4_emit_flush_rcs;  in setup_rcs()
1168 			engine->emit_flush = gen2_emit_flush;  in setup_rcs()
1170 			engine->emit_flush = gen4_emit_flush_rcs;  in setup_rcs()
1171 		engine->irq_enable_mask = I915_USER_INTERRUPT;  in setup_rcs()
1175 		engine->emit_bb_start = hsw_emit_bb_start;  in setup_rcs()
1178 static void setup_vcs(struct intel_engine_cs *engine)  in setup_vcs()  argument
1180 	struct drm_i915_private *i915 = engine->i915;  in setup_vcs()
1185 			engine->set_default_submission = gen6_bsd_set_default_submission;  in setup_vcs()
1186 		engine->emit_flush = gen6_emit_flush_vcs;  in setup_vcs()
1187 		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;  in setup_vcs()
1190 			engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;  in setup_vcs()
1192 			engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_vcs()
1194 		engine->emit_flush = gen4_emit_flush_vcs;  in setup_vcs()
1196 			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;  in setup_vcs()
1198 			engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;  in setup_vcs()
1202 static void setup_bcs(struct intel_engine_cs *engine)  in setup_bcs()  argument
1204 	struct drm_i915_private *i915 = engine->i915;  in setup_bcs()
1206 	engine->emit_flush = gen6_emit_flush_xcs;  in setup_bcs()
1207 	engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;  in setup_bcs()
1210 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;  in setup_bcs()
1212 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_bcs()
1215 static void setup_vecs(struct intel_engine_cs *engine)  in setup_vecs()  argument
1217 	struct drm_i915_private *i915 = engine->i915;  in setup_vecs()
1221 	engine->emit_flush = gen6_emit_flush_xcs;  in setup_vecs()
1222 	engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;  in setup_vecs()
1223 	engine->irq_enable = hsw_irq_enable_vecs;  in setup_vecs()
1224 	engine->irq_disable = hsw_irq_disable_vecs;  in setup_vecs()
1226 	engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_vecs()
1229 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,  in gen7_ctx_switch_bb_setup()  argument
1232 	return gen7_setup_clear_gpr_bb(engine, vma);  in gen7_ctx_switch_bb_setup()
1235 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,  in gen7_ctx_switch_bb_init()  argument
1249 	err = gen7_ctx_switch_bb_setup(engine, vma);  in gen7_ctx_switch_bb_init()
1253 	engine->wa_ctx.vma = vma;  in gen7_ctx_switch_bb_init()
1261 static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)  in gen7_ctx_vma()  argument
1267 	if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)  in gen7_ctx_vma()
1270 	err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);  in gen7_ctx_vma()
1278 	obj = i915_gem_object_create_internal(engine->i915, size);  in gen7_ctx_vma()
1282 	vma = i915_vma_instance(obj, engine->gt->vm, NULL);  in gen7_ctx_vma()
1288 	vma->private = intel_context_create(engine); /* dummy residuals */  in gen7_ctx_vma()
1299 int intel_ring_submission_setup(struct intel_engine_cs *engine)  in intel_ring_submission_setup()  argument
1307 	setup_common(engine);  in intel_ring_submission_setup()
1309 	switch (engine->class) {  in intel_ring_submission_setup()
1311 		setup_rcs(engine);  in intel_ring_submission_setup()
1314 		setup_vcs(engine);  in intel_ring_submission_setup()
1317 		setup_bcs(engine);  in intel_ring_submission_setup()
1320 		setup_vecs(engine);  in intel_ring_submission_setup()
1323 		MISSING_CASE(engine->class);  in intel_ring_submission_setup()
1327 	timeline = intel_timeline_create_from_engine(engine,  in intel_ring_submission_setup()
1335 	ring = intel_engine_create_ring(engine, SZ_16K);  in intel_ring_submission_setup()
1341 	GEM_BUG_ON(engine->legacy.ring);  in intel_ring_submission_setup()
1342 	engine->legacy.ring = ring;  in intel_ring_submission_setup()
1343 	engine->legacy.timeline = timeline;  in intel_ring_submission_setup()
1345 	gen7_wa_vma = gen7_ctx_vma(engine);  in intel_ring_submission_setup()
1357 	if (!err && engine->legacy.ring->vma->obj)  in intel_ring_submission_setup()
1358 		err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);  in intel_ring_submission_setup()
1369 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);  in intel_ring_submission_setup()
1372 		err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma);  in intel_ring_submission_setup()
1390 	engine->release = ring_release;  in intel_ring_submission_setup()
1404 	intel_engine_cleanup_common(engine);  in intel_ring_submission_setup()