Lines Matching +full:wakeup +full:- +full:latency
1 // SPDX-License-Identifier: MIT
19 * low-voltage mode when idle, using down to 0V while at this stage. This
25 * among each other with the latency required to enter and leave RC6 and
33 * require higher latency to switch to and wake up.
43 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
48 return rc6_to_gt(rc)->i915; in rc6_to_i915()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable()
68 if (!intel_uc_uses_guc_rc(>->uc)) { in gen11_rc6_enable()
76 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
90 * it takes us to service a CS interrupt and submit a new ELSP - that in gen11_rc6_enable()
93 * interrupt service latency, the hardware will automatically gate in gen11_rc6_enable()
95 * the service latency. A similar guide from plane_state is that we in gen11_rc6_enable()
96 * do not want the enable hysteresis to less than the wakeup latency. in gen11_rc6_enable()
99 * service latency, and puts it under 10us for Icelake, similar to in gen11_rc6_enable()
112 if (!intel_guc_rc_enable(>->uc.guc)) in gen11_rc6_enable()
113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; in gen11_rc6_enable()
115 rc6->ctl_enable = in gen11_rc6_enable()
125 if (GRAPHICS_VER(gt->i915) >= 12) { in gen11_rc6_enable()
158 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen9_rc6_enable()
169 * it takes us to service a CS interrupt and submit a new ELSP - that in gen9_rc6_enable()
172 * interrupt service latency, the hardware will automatically gate in gen9_rc6_enable()
174 * the service latency. A similar guide from plane_state is that we in gen9_rc6_enable()
175 * do not want the enable hysteresis to less than the wakeup latency. in gen9_rc6_enable()
178 * service latency, and puts it around 10us for Broadwell (and other in gen9_rc6_enable()
181 * However, the wakeup latency on Broxton is closer to 100us. To be in gen9_rc6_enable()
191 rc6->ctl_enable = in gen9_rc6_enable()
198 * - Render/Media PG need to be disabled with RC6. in gen9_rc6_enable()
216 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen8_rc6_enable()
221 rc6->ctl_enable = in gen8_rc6_enable()
243 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen6_rc6_enable()
257 rc6->ctl_enable = in gen6_rc6_enable()
266 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); in gen6_rc6_enable()
269 drm_dbg(&i915->drm, in gen6_rc6_enable()
270 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", in gen6_rc6_enable()
276 drm_err(&i915->drm, in gen6_rc6_enable()
292 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); in chv_rc6_init()
293 paddr = i915->dsm.end + 1 - pctx_size; in chv_rc6_init()
314 /* BIOS set it up already, grab the pre-alloc'd space */ in vlv_rc6_init()
317 pcbr_offset = (pcbr & ~4095) - i915->dsm.start; in vlv_rc6_init()
327 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); in vlv_rc6_init()
339 drm_dbg(&i915->drm, in vlv_rc6_init()
345 i915->dsm.start, in vlv_rc6_init()
346 pctx->stolen->start, in vlv_rc6_init()
348 pctx_paddr = i915->dsm.start + pctx->stolen->start; in vlv_rc6_init()
352 rc6->pctx = pctx; in vlv_rc6_init()
368 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in chv_rc6_enable()
381 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; in chv_rc6_enable()
395 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in vlv_rc6_enable()
407 rc6->ctl_enable = in vlv_rc6_enable()
422 drm_dbg(&i915->drm, "BIOS enabled RC states: " in bxt_check_bios_rc6_setup()
429 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); in bxt_check_bios_rc6_setup()
439 if (!(rc6_ctx_base >= i915->dsm_reserved.start && in bxt_check_bios_rc6_setup()
440 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) { in bxt_check_bios_rc6_setup()
441 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); in bxt_check_bios_rc6_setup()
449 drm_dbg(&i915->drm, in bxt_check_bios_rc6_setup()
457 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); in bxt_check_bios_rc6_setup()
462 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); in bxt_check_bios_rc6_setup()
467 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); in bxt_check_bios_rc6_setup()
488 drm_notice(&i915->drm, in rc6_supported()
498 GEM_BUG_ON(rc6->wakeref); in rpm_get()
499 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); in rpm_get()
500 rc6->wakeref = true; in rpm_get()
505 GEM_BUG_ON(!rc6->wakeref); in rpm_put()
506 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); in rpm_put()
507 rc6->wakeref = false; in rpm_put()
520 drm_notice(&i915->drm, in pctx_corrupted()
532 intel_guc_rc_disable(>->uc.guc); in __intel_rc6_disable()
547 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ in intel_rc6_init()
563 rc6->supported = err == 0; in intel_rc6_init()
568 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); in intel_rc6_sanitize()
570 if (rc6->enabled) { /* unbalanced suspend/resume */ in intel_rc6_sanitize()
572 rc6->enabled = false; in intel_rc6_sanitize()
575 if (rc6->supported) in intel_rc6_sanitize()
584 if (!rc6->supported) in intel_rc6_enable()
587 GEM_BUG_ON(rc6->enabled); in intel_rc6_enable()
604 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; in intel_rc6_enable()
606 rc6->ctl_enable = 0; in intel_rc6_enable()
613 /* rc6 is ready, runtime-pm is go! */ in intel_rc6_enable()
615 rc6->enabled = true; in intel_rc6_enable()
622 if (!rc6->enabled) in intel_rc6_unpark()
626 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); in intel_rc6_unpark()
634 if (!rc6->enabled) in intel_rc6_park()
642 if (!rc6->manual) in intel_rc6_park()
659 if (!rc6->enabled) in intel_rc6_disable()
663 rc6->enabled = false; in intel_rc6_disable()
674 pctx = fetch_and_zero(&rc6->pctx); in intel_rc6_fini()
678 if (rc6->wakeref) in intel_rc6_fini()
691 lockdep_assert_held(&uncore->lock); in vlv_residency_raw()
698 * Although we always use the counter in high-range mode elsewhere, in vlv_residency_raw()
716 } while (upper != tmp && --loop); in vlv_residency_raw()
720 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set in vlv_residency_raw()
737 if (!rc6->supported) in intel_rc6_residency_ns()
741 * Store previous hw counter values for counter wrap-around handling. in intel_rc6_residency_ns()
747 i = (i915_mmio_reg_offset(reg) - in intel_rc6_residency_ns()
749 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) in intel_rc6_residency_ns()
754 spin_lock_irqsave(&uncore->lock, flags); in intel_rc6_residency_ns()
760 div = i915->czclk_freq; in intel_rc6_residency_ns()
783 prev_hw = rc6->prev_hw_residency[i]; in intel_rc6_residency_ns()
784 rc6->prev_hw_residency[i] = time_hw; in intel_rc6_residency_ns()
788 time_hw -= prev_hw; in intel_rc6_residency_ns()
790 time_hw += overflow_hw - prev_hw; in intel_rc6_residency_ns()
793 time_hw += rc6->cur_residency[i]; in intel_rc6_residency_ns()
794 rc6->cur_residency[i] = time_hw; in intel_rc6_residency_ns()
797 spin_unlock_irqrestore(&uncore->lock, flags); in intel_rc6_residency_ns()