Lines Matching +full:25 +full:ns
73 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
74 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we in gen11_rc6_enable()
155 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen9_rc6_enable()
156 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen9_rc6_enable()
167 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we in gen9_rc6_enable()
213 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen8_rc6_enable()
214 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen8_rc6_enable()
240 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); in gen6_rc6_enable()
364 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in chv_rc6_enable()
365 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in chv_rc6_enable()
392 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); in vlv_rc6_enable()
764 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ in intel_rc6_residency_ns()