Lines Matching +full:0 +full:- +full:15
1 // SPDX-License-Identifier: MIT
17 ROW_INDEX_6BPP = 0,
26 COLUMN_INDEX_8BPC = 0,
58 { 768, 15, 6144, 3, 13, 11, 11, {
59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
66 { 768, 15, 6144, 7, 17, 15, 15, {
67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
71 { 17, 18, -12 }
75 { 768, 15, 6144, 11, 21, 19, 19, {
76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
80 { 21, 22, -12 }
84 { 768, 15, 6144, 15, 25, 23, 27, {
85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
89 { 25, 26, -12 }
93 { 768, 15, 6144, 19, 29, 27, 27, {
94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
98 { 29, 30, -12 }
105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
112 { 512, 12, 6144, 7, 16, 15, 15, {
113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
125 { 21, 23, -12 }
129 { 512, 12, 6144, 15, 24, 23, 23, {
130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
134 { 24, 25, -12 }
139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
143 { 28, 29, -12 }
149 { 410, 15, 5632, 3, 12, 11, 11, {
150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
157 { 410, 15, 5632, 7, 16, 15, 15, {
158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
165 { 410, 15, 5632, 11, 20, 19, 19, {
166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
170 { 19, 20, -12 }
174 { 410, 15, 5632, 15, 24, 23, 23, {
175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
179 { 23, 24, -12 }
183 { 410, 15, 5632, 19, 28, 27, 27, {
184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
188 { 27, 28, -12 }
194 { 341, 15, 2048, 3, 12, 11, 11, {
195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
202 { 341, 15, 2048, 7, 16, 15, 15, {
203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
210 { 341, 15, 2048, 11, 20, 19, 19, {
211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
215 { 21, 23, -12 }
219 { 341, 15, 2048, 15, 24, 23, 23, {
220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
224 { 22, 23, -12 }
228 { 341, 15, 2048, 19, 28, 27, 27, {
229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
233 { 26, 27, -12 }
238 /* 15BPP/8BPC */
239 { 273, 15, 2048, 3, 12, 11, 11, {
240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
246 /* 15BPP/10BPC */
247 { 273, 15, 2048, 7, 16, 15, 15, {
248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
254 /* 15BPP/12BPC */
255 { 273, 15, 2048, 11, 20, 19, 19, {
256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
260 { 16, 17, -12 }
263 /* 15BPP/14BPC */
264 { 273, 15, 2048, 15, 24, 23, 23, {
265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
269 { 20, 21, -12 }
272 /* 15BPP/16BPC */
273 { 273, 15, 2048, 19, 28, 27, 27, {
274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
278 { 24, 25, -12 }
296 case 15: in get_row_index_for_rc_params()
299 return -EINVAL; in get_row_index_for_rc_params()
317 return -EINVAL; in get_column_index_for_rc_params()
327 if (row_index < 0) in get_rc_params()
331 if (column_index < 0) in get_rc_params()
339 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_source_support()
340 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_source_support()
341 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
342 enum pipe pipe = crtc->pipe; in intel_dsc_source_support()
344 if (!INTEL_INFO(i915)->display.has_dsc) in intel_dsc_source_support()
362 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in is_pipe_dsc()
363 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); in is_pipe_dsc()
364 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in is_pipe_dsc()
375 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
384 int bpc = vdsc_cfg->bits_per_component; in calculate_rc_params()
385 int bpp = vdsc_cfg->bits_per_pixel >> 4; in calculate_rc_params()
386 int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; in calculate_rc_params()
387 int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; in calculate_rc_params()
388 int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; in calculate_rc_params()
389 int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; in calculate_rc_params()
390 int qp_bpc_modifier = (bpc - 8) * 2; in calculate_rc_params()
393 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
394 rc->first_line_bpg_offset = in calculate_rc_params()
395 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); in calculate_rc_params()
397 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
401 rc->initial_offset = 2048; in calculate_rc_params()
403 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
405 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
407 rc->initial_offset = 6144; in calculate_rc_params()
410 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); in calculate_rc_params()
412 rc->flatness_min_qp = 3 + qp_bpc_modifier; in calculate_rc_params()
413 rc->flatness_max_qp = 12 + qp_bpc_modifier; in calculate_rc_params()
415 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; in calculate_rc_params()
416 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; in calculate_rc_params()
418 bpp_i = (2 * (bpp - 6)); in calculate_rc_params()
419 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { in calculate_rc_params()
421 rc->rc_range_params[buf_i].range_min_qp = in calculate_rc_params()
423 rc->rc_range_params[buf_i].range_max_qp = in calculate_rc_params()
428 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; in calculate_rc_params()
430 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); in calculate_rc_params()
431 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
434 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
436 } else if (bpp <= 15) { in calculate_rc_params()
437 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); in calculate_rc_params()
438 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
441 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsc_compute_params()
451 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
452 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
455 u8 i = 0; in intel_dsc_compute_params()
457 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
458 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_dsc_compute_params()
459 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
460 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
463 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
465 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
468 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()
469 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
471 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_compute_params()
473 * six 0s are appended to the lsb of each threshold value in intel_dsc_compute_params()
477 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; in intel_dsc_compute_params()
485 vdsc_cfg->rc_buf_thresh[12] = 0x7C; in intel_dsc_compute_params()
486 vdsc_cfg->rc_buf_thresh[13] = 0x7D; in intel_dsc_compute_params()
491 * upto uncompressed bpp-1, hence add calculations for all the rc in intel_dsc_compute_params()
497 return -ENOMEM; in intel_dsc_compute_params()
503 vdsc_cfg->bits_per_component); in intel_dsc_compute_params()
505 return -EINVAL; in intel_dsc_compute_params()
508 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; in intel_dsc_compute_params()
509 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; in intel_dsc_compute_params()
510 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()
511 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; in intel_dsc_compute_params()
512 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; in intel_dsc_compute_params()
513 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; in intel_dsc_compute_params()
514 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; in intel_dsc_compute_params()
516 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_compute_params()
517 vdsc_cfg->rc_range_params[i].range_min_qp = in intel_dsc_compute_params()
518 rc_params->rc_range_params[i].range_min_qp; in intel_dsc_compute_params()
519 vdsc_cfg->rc_range_params[i].range_max_qp = in intel_dsc_compute_params()
520 rc_params->rc_range_params[i].range_max_qp; in intel_dsc_compute_params()
525 vdsc_cfg->rc_range_params[i].range_bpg_offset = in intel_dsc_compute_params()
526 rc_params->rc_range_params[i].range_bpg_offset & in intel_dsc_compute_params()
535 if (vdsc_cfg->bits_per_component <= 10) in intel_dsc_compute_params()
536 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in intel_dsc_compute_params()
538 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; in intel_dsc_compute_params()
541 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()
542 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
546 return 0; in intel_dsc_compute_params()
552 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_power_domain()
553 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_power_domain()
554 enum pipe pipe = crtc->pipe; in intel_dsc_power_domain()
560 * - ICL eDP/DSI transcoder in intel_dsc_power_domain()
561 * - Display version 12 (except RKL) pipe A in intel_dsc_power_domain()
577 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_pps_configure()
578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_pps_configure()
579 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
580 enum pipe pipe = crtc->pipe; in intel_dsc_pps_configure()
581 u32 pps_val = 0; in intel_dsc_pps_configure()
584 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; in intel_dsc_pps_configure()
585 int i = 0; in intel_dsc_pps_configure()
587 if (crtc_state->bigjoiner) in intel_dsc_pps_configure()
591 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << in intel_dsc_pps_configure()
593 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | in intel_dsc_pps_configure()
594 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; in intel_dsc_pps_configure()
595 if (vdsc_cfg->block_pred_enable) in intel_dsc_pps_configure()
597 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()
599 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()
601 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()
603 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
611 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
618 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
625 pps_val = 0; in intel_dsc_pps_configure()
626 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure()
627 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
635 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
642 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
649 pps_val = 0; in intel_dsc_pps_configure()
650 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
651 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
652 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
660 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
667 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
674 pps_val = 0; in intel_dsc_pps_configure()
675 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
676 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
677 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
685 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
692 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
699 pps_val = 0; in intel_dsc_pps_configure()
700 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | in intel_dsc_pps_configure()
701 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); in intel_dsc_pps_configure()
702 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
710 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
717 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
724 pps_val = 0; in intel_dsc_pps_configure()
725 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | in intel_dsc_pps_configure()
726 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); in intel_dsc_pps_configure()
727 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
735 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
742 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
749 pps_val = 0; in intel_dsc_pps_configure()
750 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | in intel_dsc_pps_configure()
751 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | in intel_dsc_pps_configure()
752 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | in intel_dsc_pps_configure()
753 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); in intel_dsc_pps_configure()
754 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
762 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
769 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
776 pps_val = 0; in intel_dsc_pps_configure()
777 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | in intel_dsc_pps_configure()
778 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); in intel_dsc_pps_configure()
779 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
787 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
794 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
801 pps_val = 0; in intel_dsc_pps_configure()
802 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
803 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
804 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
812 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
819 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
826 pps_val = 0; in intel_dsc_pps_configure()
827 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | in intel_dsc_pps_configure()
829 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
837 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
844 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
851 pps_val = 0; in intel_dsc_pps_configure()
852 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
853 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
856 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
864 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
871 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
878 pps_val = 0; in intel_dsc_pps_configure()
879 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
880 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
881 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
882 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
883 vdsc_cfg->slice_height); in intel_dsc_pps_configure()
884 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
892 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
899 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
906 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); in intel_dsc_pps_configure()
907 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_pps_configure()
909 (u32)(vdsc_cfg->rc_buf_thresh[i] << in intel_dsc_pps_configure()
911 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, in intel_dsc_pps_configure()
916 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
923 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
925 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
935 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
942 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
945 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
959 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); in intel_dsc_pps_configure()
960 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_pps_configure()
962 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
964 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
966 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
968 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, in intel_dsc_pps_configure()
973 rc_range_params_dword[0]); in intel_dsc_pps_configure()
988 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
990 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1012 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1031 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
1034 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1063 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dsi_pps_write()
1071 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsc_dsi_pps_write()
1072 dsi = intel_dsi->dsi_hosts[port]->device; in intel_dsc_dsi_pps_write()
1084 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dp_pps_write()
1087 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ in intel_dsc_dp_pps_write()
1090 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ in intel_dsc_dp_pps_write()
1093 dig_port->write_infoframe(encoder, crtc_state, in intel_dsc_dp_pps_write()
1100 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dss_ctl1_reg()
1107 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dss_ctl2_reg()
1124 return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1); in intel_dsc_get_bigjoiner_secondary()
1130 return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1); in intel_dsc_get_bigjoiner_primary()
1135 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_uncompressed_joiner_enable()
1136 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_uncompressed_joiner_enable()
1137 u32 dss_ctl1_val = 0; in intel_uncompressed_joiner_enable()
1139 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { in intel_uncompressed_joiner_enable()
1140 if (crtc_state->bigjoiner_slave) in intel_uncompressed_joiner_enable()
1152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_enable()
1153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_enable()
1154 u32 dss_ctl1_val = 0; in intel_dsc_enable()
1155 u32 dss_ctl2_val = 0; in intel_dsc_enable()
1157 if (!crtc_state->dsc.compression_enable) in intel_dsc_enable()
1162 if (!crtc_state->bigjoiner_slave) { in intel_dsc_enable()
1170 if (crtc_state->dsc.dsc_split) { in intel_dsc_enable()
1174 if (crtc_state->bigjoiner) { in intel_dsc_enable()
1176 if (!crtc_state->bigjoiner_slave) in intel_dsc_enable()
1185 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_dsc_disable()
1186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_disable()
1189 if (old_crtc_state->dsc.compression_enable || in intel_dsc_disable()
1190 old_crtc_state->bigjoiner) { in intel_dsc_disable()
1191 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); in intel_dsc_disable()
1192 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); in intel_dsc_disable()
1198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_uncompressed_joiner_get_config()
1199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_uncompressed_joiner_get_config()
1204 crtc_state->bigjoiner = true; in intel_uncompressed_joiner_get_config()
1205 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); in intel_uncompressed_joiner_get_config()
1206 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); in intel_uncompressed_joiner_get_config()
1208 crtc_state->bigjoiner = true; in intel_uncompressed_joiner_get_config()
1209 crtc_state->bigjoiner_slave = true; in intel_uncompressed_joiner_get_config()
1210 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); in intel_uncompressed_joiner_get_config()
1211 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); in intel_uncompressed_joiner_get_config()
1217 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_get_config()
1218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_get_config()
1219 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_get_config()
1220 enum pipe pipe = crtc->pipe; in intel_dsc_get_config()
1237 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; in intel_dsc_get_config()
1238 if (!crtc_state->dsc.compression_enable) in intel_dsc_get_config()
1241 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && in intel_dsc_get_config()
1245 crtc_state->bigjoiner = true; in intel_dsc_get_config()
1248 crtc_state->bigjoiner_slave = true; in intel_dsc_get_config()
1249 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); in intel_dsc_get_config()
1251 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); in intel_dsc_get_config()
1253 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); in intel_dsc_get_config()
1264 vdsc_cfg->bits_per_pixel = val; in intel_dsc_get_config()
1265 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; in intel_dsc_get_config()