Lines Matching +full:5 +full:vs
54 /* VS 0, pre-emph 0 */
57 /* VS 0, pre-emph 1 */
61 /* VS 0, pre-emph 2 */
65 /* VS 0, pre-emph 3 */
69 /* VS 1, pre-emph 0 */
72 /* VS 1, pre-emph 1 */
76 /* VS 1, pre-emph 2 */
80 /* VS 2, pre-emph 0 */
83 /* VS 2, pre-emph 1 */
87 /* VS 3, pre-emph 0 */
132 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
218 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
244 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
270 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
346 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
409 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
440 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
472 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
478 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
501 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
507 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
517 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
547 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
577 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
717 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ in intel_mpllb_enable()
735 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) in intel_mpllb_enable()
773 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment in intel_mpllb_disable()
776 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5)) in intel_mpllb_disable()