114 	enum transcoder trans_shift;  in psr_irq_control()
125 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in psr_irq_control()
127 		trans_shift = intel_dp->psr.transcoder;  in psr_irq_control()
183 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_irq_handler()
186 	enum transcoder trans_shift;  in intel_psr_irq_handler()
191 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in intel_psr_irq_handler()
193 		trans_shift = intel_dp->psr.transcoder;  in intel_psr_irq_handler()
387 			       EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),  in hsw_psr_setup_aux()
398 	intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),  in hsw_psr_setup_aux()
509 	val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &  in hsw_activate_psr1()
511 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr1()
605 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),  in hsw_activate_psr2()
609 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
616 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
618 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr2()
622 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)  in transcoder_has_psr2()
648 	val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));  in psr2_program_idle_frames()
651 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in psr2_program_idle_frames()
1074 		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));  in intel_psr_get_config()
1080 		val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));  in intel_psr_get_config()
1091 	enum transcoder transcoder = intel_dp->psr.transcoder;  in intel_psr_activate()  local
1093 	if (transcoder_has_psr2(dev_priv, transcoder))  in intel_psr_activate()
1095 			    intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);  in intel_psr_activate()
1098 		    intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);  in intel_psr_activate()
1114 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_enable_source()
1146 	intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1174 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1194 				    TRANS_PSR_IIR(intel_dp->psr.transcoder));  in psr_interrupt_error_check()
1198 		val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);  in psr_interrupt_error_check()
1225 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;  in intel_psr_enable_locked()
1284 		if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {  in intel_psr_exit()
1286 					    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1291 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1300 				    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1304 			       EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1307 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1311 			       EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1323 		psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1326 		psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1363 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_disable_locked()
1810 					 EDP_PSR_STATUS(intel_dp->psr.transcoder),  in psr_wait_for_idle()
1862 		reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()
1865 		reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()