Lines Matching refs:pp_div
354 i915_reg_t pp_div; member
378 regs->pp_div = INVALID_MMIO_REG; in intel_pps_get_registers()
380 regs->pp_div = PP_DIVISOR(pps_idx); in intel_pps_get_registers()
1121 if (i915_mmio_reg_valid(regs.pp_div)) { in intel_pps_readout_hw_state()
1122 u32 pp_div; in intel_pps_readout_hw_state() local
1124 pp_div = intel_de_read(dev_priv, regs.pp_div); in intel_pps_readout_hw_state()
1126 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1325 if (i915_mmio_reg_valid(regs.pp_div)) { in pps_init_registers()
1326 intel_de_write(dev_priv, regs.pp_div, in pps_init_registers()
1341 i915_mmio_reg_valid(regs.pp_div) ? in pps_init_registers()
1342 intel_de_read(dev_priv, regs.pp_div) : in pps_init_registers()