Lines Matching +full:vdd +full:- +full:s
1 // SPDX-License-Identifier: MIT
29 mutex_lock(&dev_priv->pps_mutex); in intel_pps_lock()
39 mutex_unlock(&dev_priv->pps_mutex); in intel_pps_unlock()
50 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_power_sequencer_kick()
56 if (drm_WARN(&dev_priv->drm, in vlv_power_sequencer_kick()
57 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
58 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", in vlv_power_sequencer_kick()
59 pipe_name(pipe), dig_port->base.base.base.id, in vlv_power_sequencer_kick()
60 dig_port->base.base.name)) in vlv_power_sequencer_kick()
63 drm_dbg_kms(&dev_priv->drm, in vlv_power_sequencer_kick()
64 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", in vlv_power_sequencer_kick()
65 pipe_name(pipe), dig_port->base.base.base.id, in vlv_power_sequencer_kick()
66 dig_port->base.base.name); in vlv_power_sequencer_kick()
68 /* Preserve the BIOS-computed detected bit. This is in vlv_power_sequencer_kick()
69 * supposed to be read-only. in vlv_power_sequencer_kick()
71 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
85 * So enable temporarily it if it's not already enabled. in vlv_power_sequencer_kick()
92 drm_err(&dev_priv->drm, in vlv_power_sequencer_kick()
103 * Otherwise even VDD force bit won't work. in vlv_power_sequencer_kick()
105 intel_de_write(dev_priv, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
106 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
108 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
109 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
111 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
112 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
129 * Pick one that's not used by other ports. in vlv_find_free_pps()
131 for_each_intel_dp(&dev_priv->drm, encoder) { in vlv_find_free_pps()
134 if (encoder->type == INTEL_OUTPUT_EDP) { in vlv_find_free_pps()
135 drm_WARN_ON(&dev_priv->drm, in vlv_find_free_pps()
136 intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_find_free_pps()
137 intel_dp->pps.active_pipe != in vlv_find_free_pps()
138 intel_dp->pps.pps_pipe); in vlv_find_free_pps()
140 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_find_free_pps()
141 pipes &= ~(1 << intel_dp->pps.pps_pipe); in vlv_find_free_pps()
143 drm_WARN_ON(&dev_priv->drm, in vlv_find_free_pps()
144 intel_dp->pps.pps_pipe != INVALID_PIPE); in vlv_find_free_pps()
146 if (intel_dp->pps.active_pipe != INVALID_PIPE) in vlv_find_free_pps()
147 pipes &= ~(1 << intel_dp->pps.active_pipe); in vlv_find_free_pps()
154 return ffs(pipes) - 1; in vlv_find_free_pps()
164 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_power_sequencer_pipe()
167 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
169 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
170 intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe); in vlv_power_sequencer_pipe()
172 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_power_sequencer_pipe()
173 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
181 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
185 intel_dp->pps.pps_pipe = pipe; in vlv_power_sequencer_pipe()
187 drm_dbg_kms(&dev_priv->drm, in vlv_power_sequencer_pipe()
188 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", in vlv_power_sequencer_pipe()
189 pipe_name(intel_dp->pps.pps_pipe), in vlv_power_sequencer_pipe()
190 dig_port->base.base.base.id, in vlv_power_sequencer_pipe()
191 dig_port->base.base.name); in vlv_power_sequencer_pipe()
198 * Even vdd force doesn't work until we've made in vlv_power_sequencer_pipe()
203 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
210 int backlight_controller = dev_priv->vbt.backlight.controller; in bxt_power_sequencer_idx()
212 lockdep_assert_held(&dev_priv->pps_mutex); in bxt_power_sequencer_idx()
215 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
217 if (!intel_dp->pps.pps_reset) in bxt_power_sequencer_idx()
220 intel_dp->pps.pps_reset = false; in bxt_power_sequencer_idx()
280 enum port port = dig_port->base.port; in vlv_initial_power_sequencer_setup()
282 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_initial_power_sequencer_setup()
286 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
288 /* didn't find one? pick one where vdd is on */ in vlv_initial_power_sequencer_setup()
289 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
290 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
293 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
294 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
298 if (intel_dp->pps.pps_pipe == INVALID_PIPE) { in vlv_initial_power_sequencer_setup()
299 drm_dbg_kms(&dev_priv->drm, in vlv_initial_power_sequencer_setup()
300 "no initial power sequencer for [ENCODER:%d:%s]\n", in vlv_initial_power_sequencer_setup()
301 dig_port->base.base.base.id, in vlv_initial_power_sequencer_setup()
302 dig_port->base.base.name); in vlv_initial_power_sequencer_setup()
306 drm_dbg_kms(&dev_priv->drm, in vlv_initial_power_sequencer_setup()
307 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", in vlv_initial_power_sequencer_setup()
308 dig_port->base.base.base.id, in vlv_initial_power_sequencer_setup()
309 dig_port->base.base.name, in vlv_initial_power_sequencer_setup()
310 pipe_name(intel_dp->pps.pps_pipe)); in vlv_initial_power_sequencer_setup()
317 if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv))) in intel_pps_reset_all()
333 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_pps_reset_all()
336 drm_WARN_ON(&dev_priv->drm, in intel_pps_reset_all()
337 intel_dp->pps.active_pipe != INVALID_PIPE); in intel_pps_reset_all()
339 if (encoder->type != INTEL_OUTPUT_EDP) in intel_pps_reset_all()
343 intel_dp->pps.pps_reset = true; in intel_pps_reset_all()
345 intel_dp->pps.pps_pipe = INVALID_PIPE; in intel_pps_reset_all()
370 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
371 regs->pp_stat = PP_STATUS(pps_idx); in intel_pps_get_registers()
372 regs->pp_on = PP_ON_DELAYS(pps_idx); in intel_pps_get_registers()
373 regs->pp_off = PP_OFF_DELAYS(pps_idx); in intel_pps_get_registers()
378 regs->pp_div = INVALID_MMIO_REG; in intel_pps_get_registers()
380 regs->pp_div = PP_DIVISOR(pps_idx); in intel_pps_get_registers()
407 lockdep_assert_held(&dev_priv->pps_mutex); in edp_have_panel_power()
410 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_power()
420 lockdep_assert_held(&dev_priv->pps_mutex); in edp_have_panel_vdd()
423 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_vdd()
437 drm_WARN(&dev_priv->drm, 1, in intel_pps_check_power_unlocked()
439 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", in intel_pps_check_power_unlocked()
463 lockdep_assert_held(&dev_priv->pps_mutex); in wait_panel_status()
470 drm_dbg_kms(&dev_priv->drm, in wait_panel_status()
478 drm_err(&dev_priv->drm, in wait_panel_status()
483 drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); in wait_panel_status()
490 drm_dbg_kms(&i915->drm, "Wait for panel power on\n"); in wait_panel_on()
498 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n"); in wait_panel_off()
508 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n"); in wait_panel_power_cycle()
513 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); in wait_panel_power_cycle()
515 /* When we disable the VDD override bit last we have to do the manual in wait_panel_power_cycle()
517 if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay) in wait_panel_power_cycle()
519 intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); in wait_panel_power_cycle()
537 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, in wait_backlight_on()
538 intel_dp->pps.backlight_on_delay); in wait_backlight_on()
543 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, in edp_wait_backlight_off()
544 intel_dp->pps.backlight_off_delay); in edp_wait_backlight_off()
556 lockdep_assert_held(&dev_priv->pps_mutex); in ilk_get_pp_control()
559 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && in ilk_get_pp_control()
578 bool need_to_disable = !intel_dp->pps.want_panel_vdd; in intel_pps_vdd_on_unlocked()
580 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_vdd_on_unlocked()
585 cancel_delayed_work(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_on_unlocked()
586 intel_dp->pps.want_panel_vdd = true; in intel_pps_vdd_on_unlocked()
591 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
592 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in intel_pps_vdd_on_unlocked()
595 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", in intel_pps_vdd_on_unlocked()
596 dig_port->base.base.base.id, in intel_pps_vdd_on_unlocked()
597 dig_port->base.base.name); in intel_pps_vdd_on_unlocked()
610 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_on_unlocked()
617 drm_dbg_kms(&dev_priv->drm, in intel_pps_vdd_on_unlocked()
618 "[ENCODER:%d:%s] panel power wasn't enabled\n", in intel_pps_vdd_on_unlocked()
619 dig_port->base.base.base.id, in intel_pps_vdd_on_unlocked()
620 dig_port->base.base.name); in intel_pps_vdd_on_unlocked()
621 msleep(intel_dp->pps.panel_power_up_delay); in intel_pps_vdd_on_unlocked()
636 bool vdd; in intel_pps_vdd_on() local
641 vdd = false; in intel_pps_vdd_on()
643 vdd = intel_pps_vdd_on_unlocked(intel_dp); in intel_pps_vdd_on()
644 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n", in intel_pps_vdd_on()
645 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_on()
646 dp_to_dig_port(intel_dp)->base.base.name); in intel_pps_vdd_on()
657 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_vdd_off_sync_unlocked()
659 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
664 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", in intel_pps_vdd_off_sync_unlocked()
665 dig_port->base.base.base.id, in intel_pps_vdd_off_sync_unlocked()
666 dig_port->base.base.name); in intel_pps_vdd_off_sync_unlocked()
678 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_off_sync_unlocked()
683 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_vdd_off_sync_unlocked()
687 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_vdd_off_sync_unlocked()
697 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_off_sync()
699 * vdd might still be enabled due to the delayed vdd off. in intel_pps_vdd_off_sync()
700 * Make sure vdd is actually turned off here. in intel_pps_vdd_off_sync()
714 if (!intel_dp->pps.want_panel_vdd) in edp_panel_vdd_work()
728 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5); in edp_panel_vdd_schedule_off()
729 schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay); in edp_panel_vdd_schedule_off()
741 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_vdd_off_unlocked()
746 I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on", in intel_pps_vdd_off_unlocked()
747 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_off_unlocked()
748 dp_to_dig_port(intel_dp)->base.base.name); in intel_pps_vdd_off_unlocked()
750 intel_dp->pps.want_panel_vdd = false; in intel_pps_vdd_off_unlocked()
764 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_on_unlocked()
769 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", in intel_pps_on_unlocked()
770 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
771 dp_to_dig_port(intel_dp)->base.base.name); in intel_pps_on_unlocked()
773 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
774 "[ENCODER:%d:%s] panel power already on\n", in intel_pps_on_unlocked()
775 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
776 dp_to_dig_port(intel_dp)->base.base.name)) in intel_pps_on_unlocked()
798 intel_dp->pps.last_power_on = jiffies; in intel_pps_on_unlocked()
825 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_off_unlocked()
830 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", in intel_pps_off_unlocked()
831 dig_port->base.base.base.id, dig_port->base.base.name); in intel_pps_off_unlocked()
833 drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
834 "Need [ENCODER:%d:%s] VDD to turn off panel\n", in intel_pps_off_unlocked()
835 dig_port->base.base.base.id, dig_port->base.base.name); in intel_pps_off_unlocked()
838 /* We need to switch off panel power _and_ force vdd, for otherwise some in intel_pps_off_unlocked()
845 intel_dp->pps.want_panel_vdd = false; in intel_pps_off_unlocked()
851 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_off_unlocked()
853 /* We got a reference when we enabled the VDD. */ in intel_pps_off_unlocked()
856 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_off_unlocked()
916 intel_dp->pps.last_backlight_off = jiffies; in intel_pps_backlight_off()
926 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_pps_backlight_power()
937 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
949 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in vlv_detach_power_sequencer()
950 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_detach_power_sequencer()
953 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
955 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
962 * have the same port selected (even if only one has power/vdd in vlv_detach_power_sequencer()
965 * selected in multiple power sequencers, but let's clear the in vlv_detach_power_sequencer()
969 drm_dbg_kms(&dev_priv->drm, in vlv_detach_power_sequencer()
970 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", in vlv_detach_power_sequencer()
971 pipe_name(pipe), dig_port->base.base.base.id, in vlv_detach_power_sequencer()
972 dig_port->base.base.name); in vlv_detach_power_sequencer()
976 intel_dp->pps.pps_pipe = INVALID_PIPE; in vlv_detach_power_sequencer()
984 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_steal_power_sequencer()
986 for_each_intel_dp(&dev_priv->drm, encoder) { in vlv_steal_power_sequencer()
989 drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe, in vlv_steal_power_sequencer()
990 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", in vlv_steal_power_sequencer()
991 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
992 encoder->base.name); in vlv_steal_power_sequencer()
994 if (intel_dp->pps.pps_pipe != pipe) in vlv_steal_power_sequencer()
997 drm_dbg_kms(&dev_priv->drm, in vlv_steal_power_sequencer()
998 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", in vlv_steal_power_sequencer()
999 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1000 encoder->base.name); in vlv_steal_power_sequencer()
1002 /* make sure vdd is off before we steal it */ in vlv_steal_power_sequencer()
1010 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_pps_init()
1012 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_pps_init()
1014 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_pps_init()
1016 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_pps_init()
1018 if (intel_dp->pps.pps_pipe != INVALID_PIPE && in vlv_pps_init()
1019 intel_dp->pps.pps_pipe != crtc->pipe) { in vlv_pps_init()
1022 * port previously make sure to turn off vdd there while in vlv_pps_init()
1032 vlv_steal_power_sequencer(dev_priv, crtc->pipe); in vlv_pps_init()
1034 intel_dp->pps.active_pipe = crtc->pipe; in vlv_pps_init()
1039 /* now it's all ours */ in vlv_pps_init()
1040 intel_dp->pps.pps_pipe = crtc->pipe; in vlv_pps_init()
1042 drm_dbg_kms(&dev_priv->drm, in vlv_pps_init()
1043 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", in vlv_pps_init()
1044 pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id, in vlv_pps_init()
1045 encoder->base.name); in vlv_pps_init()
1057 lockdep_assert_held(&dev_priv->pps_mutex); in intel_pps_vdd_sanitize()
1063 * The VDD bit needs a power domain reference, so if the bit is in intel_pps_vdd_sanitize()
1065 * schedule a vdd off, so we don't hold on to the reference in intel_pps_vdd_sanitize()
1068 drm_dbg_kms(&dev_priv->drm, in intel_pps_vdd_sanitize()
1069 "VDD left on by BIOS, adjusting state tracking\n"); in intel_pps_vdd_sanitize()
1070 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_sanitize()
1071 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in intel_pps_vdd_sanitize()
1092 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in pps_init_timestamps()
1093 intel_dp->pps.last_power_on = jiffies; in pps_init_timestamps()
1094 intel_dp->pps.last_backlight_off = jiffies; in pps_init_timestamps()
1116 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1117 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1118 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1119 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1126 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1128 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
1135 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", in intel_pps_dump_state()
1137 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1144 struct edp_power_seq *sw = &intel_dp->pps.pps_delays; in intel_pps_verify_state()
1148 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1149 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { in intel_pps_verify_state()
1160 *final = &intel_dp->pps.pps_delays; in pps_init_delays()
1162 lockdep_assert_held(&dev_priv->pps_mutex); in pps_init_delays()
1165 if (final->t11_t12 != 0) in pps_init_delays()
1172 vbt = dev_priv->vbt.edp.pps; in pps_init_delays()
1173 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay in pps_init_delays()
1178 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { in pps_init_delays()
1180 drm_dbg_kms(&dev_priv->drm, in pps_init_delays()
1206 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ in pps_init_delays()
1216 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) in pps_init_delays()
1217 intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); in pps_init_delays()
1218 intel_dp->pps.backlight_on_delay = get_delay(t8); in pps_init_delays()
1219 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1220 intel_dp->pps.panel_power_down_delay = get_delay(t10); in pps_init_delays()
1221 intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); in pps_init_delays()
1224 drm_dbg_kms(&dev_priv->drm, in pps_init_delays()
1226 intel_dp->pps.panel_power_up_delay, in pps_init_delays()
1227 intel_dp->pps.panel_power_down_delay, in pps_init_delays()
1228 intel_dp->pps.panel_power_cycle_delay); in pps_init_delays()
1230 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1231 intel_dp->pps.backlight_on_delay, in pps_init_delays()
1232 intel_dp->pps.backlight_off_delay); in pps_init_delays()
1241 final->t8 = 1; in pps_init_delays()
1242 final->t9 = 1; in pps_init_delays()
1248 final->t11_t12 = roundup(final->t11_t12, 100 * 10); in pps_init_delays()
1255 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; in pps_init_registers()
1257 enum port port = dp_to_dig_port(intel_dp)->base.port; in pps_init_registers()
1258 const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; in pps_init_registers()
1260 lockdep_assert_held(&dev_priv->pps_mutex); in pps_init_registers()
1265 * On some VLV machines the BIOS can leave the VDD in pps_init_registers()
1270 * intel_pps_vdd_on_unlocked() would notice that the VDD was in pps_init_registers()
1272 * domain reference. Disable VDD first to avoid this. in pps_init_registers()
1273 * This also avoids spuriously turning the VDD on as in pps_init_registers()
1279 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1283 drm_dbg_kms(&dev_priv->drm, in pps_init_registers()
1284 "VDD already on, disabling first\n"); in pps_init_registers()
1291 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1292 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1293 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1294 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1327 …P_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_… in pps_init_registers()
1333 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in pps_init_registers()
1337 drm_dbg_kms(&dev_priv->drm, in pps_init_registers()
1371 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); in intel_pps_init()
1405 i915->pps_mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1407 i915->pps_mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1409 i915->pps_mmio_base = PPS_BASE; in intel_pps_setup()