Lines Matching +full:panel +full:- +full:lvds
2 * Copyright © 2006-2007 Intel Corporation
50 /* Private structure for the integrated LVDS support */
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
103 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_hw_state()
108 encoder->power_domain); in intel_lvds_get_hw_state()
112 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
123 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_config()
126 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
128 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
138 pipe_config->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
141 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
148 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
151 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
159 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
162 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
163 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
164 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
175 * too short power-cycle delay due to the asynchronous programming of in intel_lvds_pps_get_hw_state()
179 val--; in intel_lvds_pps_get_hw_state()
181 pps->t4 = val * 1000; in intel_lvds_pps_get_hw_state()
184 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { in intel_lvds_pps_get_hw_state()
185 drm_dbg_kms(&dev_priv->drm, in intel_lvds_pps_get_hw_state()
186 "Panel power timings uninitialized, " in intel_lvds_pps_get_hw_state()
189 pps->t1_t2 = 40 * 10; in intel_lvds_pps_get_hw_state()
190 pps->t5 = 200 * 10; in intel_lvds_pps_get_hw_state()
192 pps->t3 = 35 * 10; in intel_lvds_pps_get_hw_state()
193 pps->tx = 200 * 10; in intel_lvds_pps_get_hw_state()
196 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " in intel_lvds_pps_get_hw_state()
198 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, in intel_lvds_pps_get_hw_state()
199 pps->divider, pps->port, pps->powerdown_on_reset); in intel_lvds_pps_get_hw_state()
208 drm_WARN_ON(&dev_priv->drm, in intel_lvds_pps_init_hw()
210 if (pps->powerdown_on_reset) in intel_lvds_pps_init_hw()
215 …ORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PR… in intel_lvds_pps_init_hw()
218 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, … in intel_lvds_pps_init_hw()
221 …ELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, D… in intel_lvds_pps_init_hw()
229 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_pre_enable_lvds()
230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_pre_enable_lvds()
231 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pre_enable_lvds()
232 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_pre_enable_lvds()
233 enum pipe pipe = crtc->pipe; in intel_pre_enable_lvds()
239 pipe_config->shared_dpll); in intel_pre_enable_lvds()
244 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); in intel_pre_enable_lvds()
246 temp = lvds_encoder->init_lvds_val; in intel_pre_enable_lvds()
259 temp |= pipe_config->gmch_pfit.lvds_border_bits; in intel_pre_enable_lvds()
262 * Set the B0-B3 data pairs corresponding to whether we're going to in intel_pre_enable_lvds()
263 * set the DPLLs for dual-channel mode or not. in intel_pre_enable_lvds()
265 if (lvds_encoder->is_dual_link) in intel_pre_enable_lvds()
271 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in intel_pre_enable_lvds()
277 temp |= lvds_encoder->a3_power; in intel_pre_enable_lvds()
280 * Set the dithering flag on LVDS as needed, note that there is no in intel_pre_enable_lvds()
281 * special lvds dither control bit on pch-split platforms, dithering is in intel_pre_enable_lvds()
286 * Bspec wording suggests that LVDS port dithering only exists in intel_pre_enable_lvds()
289 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
295 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in intel_pre_enable_lvds()
297 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in intel_pre_enable_lvds()
300 intel_de_write(dev_priv, lvds_encoder->reg, temp); in intel_pre_enable_lvds()
304 * Sets the power state for the panel.
311 struct drm_device *dev = encoder->base.dev; in intel_enable_lvds()
312 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_enable_lvds()
315 intel_de_write(dev_priv, lvds_encoder->reg, in intel_enable_lvds()
316 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
320 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
323 drm_err(&dev_priv->drm, in intel_enable_lvds()
324 "timed out waiting for panel to power on\n"); in intel_enable_lvds()
334 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_disable_lvds()
335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_lvds()
340 drm_err(&dev_priv->drm, in intel_disable_lvds()
341 "timed out waiting for panel to power off\n"); in intel_disable_lvds()
343 intel_de_write(dev_priv, lvds_encoder->reg, in intel_disable_lvds()
344 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
345 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_shutdown()
380 drm_err(&dev_priv->drm, in intel_lvds_shutdown()
381 "timed out waiting for panel power cycle delay\n"); in intel_lvds_shutdown()
389 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; in intel_lvds_mode_valid()
390 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; in intel_lvds_mode_valid()
392 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_mode_valid()
394 if (mode->hdisplay > fixed_mode->hdisplay) in intel_lvds_mode_valid()
396 if (mode->vdisplay > fixed_mode->vdisplay) in intel_lvds_mode_valid()
398 if (fixed_mode->clock > max_pixclk) in intel_lvds_mode_valid()
408 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); in intel_lvds_compute_config()
410 to_lvds_encoder(&intel_encoder->base); in intel_lvds_compute_config()
412 lvds_encoder->attached_connector; in intel_lvds_compute_config()
413 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_lvds_compute_config()
414 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_lvds_compute_config()
419 if (DISPLAY_VER(dev_priv) < 4 && crtc->pipe == 0) { in intel_lvds_compute_config()
420 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); in intel_lvds_compute_config()
421 return -EINVAL; in intel_lvds_compute_config()
424 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) in intel_lvds_compute_config()
429 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
430 drm_dbg_kms(&dev_priv->drm, in intel_lvds_compute_config()
431 "forcing display bpp (was %d) to LVDS (%d)\n", in intel_lvds_compute_config()
432 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
433 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
436 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_lvds_compute_config()
439 * We have timings from the BIOS for the panel, put them in in intel_lvds_compute_config()
441 * with the panel scaling set up to source from the H/VDisplay in intel_lvds_compute_config()
444 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, in intel_lvds_compute_config()
447 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_compute_config()
448 return -EINVAL; in intel_lvds_compute_config()
451 pipe_config->has_pch_encoder = true; in intel_lvds_compute_config()
475 struct drm_device *dev = connector->dev; in intel_lvds_get_modes()
479 if (!IS_ERR_OR_NULL(intel_connector->edid)) in intel_lvds_get_modes()
480 return drm_add_edid_modes(connector, intel_connector->edid); in intel_lvds_get_modes()
482 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); in intel_lvds_get_modes()
514 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); in intel_no_lvds_dmi_callback()
518 /* These systems claim to have LVDS, but really don't */
538 .ident = "MSI IM-945GSE-A",
565 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
573 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
578 .ident = "AOpen i915GMm-HFS",
581 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
586 .ident = "AOpen i45GMx-I",
589 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
594 .ident = "Aopen i945GTt-VFA",
625 .ident = "Asus AT5NM10T-I",
628 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
633 .ident = "Hewlett-Packard HP t5740",
635 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
641 .ident = "Hewlett-Packard t5745",
643 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
649 .ident = "Hewlett-Packard st5747",
651 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
659 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
660 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
665 .ident = "Gigabyte GA-D525TUD",
673 .ident = "Supermicro X7SPA-H",
676 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
733 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); in intel_dual_link_lvds_callback()
769 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_get_lvds_encoder()
770 if (encoder->type == INTEL_OUTPUT_LVDS) in intel_get_lvds_encoder()
781 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; in intel_is_dual_link_lvds()
786 struct drm_device *dev = lvds_encoder->base.base.dev; in compute_is_dual_link_lvds()
791 if (dev_priv->params.lvds_channel_mode > 0) in compute_is_dual_link_lvds()
792 return dev_priv->params.lvds_channel_mode == 2; in compute_is_dual_link_lvds()
794 /* single channel LVDS is limited to 112 MHz */ in compute_is_dual_link_lvds()
795 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) in compute_is_dual_link_lvds()
802 * BIOS should set the proper LVDS register value at boot, but in compute_is_dual_link_lvds()
804 * we need to check "the value to be set" in VBT when LVDS in compute_is_dual_link_lvds()
807 val = intel_de_read(dev_priv, lvds_encoder->reg); in compute_is_dual_link_lvds()
813 val = dev_priv->vbt.bios_lvds_val; in compute_is_dual_link_lvds()
819 * intel_lvds_init - setup LVDS connectors on this device
822 * Create the connector, register the LVDS DDC bus, and try to figure out what
823 * modes we can display on the LVDS panel (if present).
827 struct drm_device *dev = &dev_priv->drm; in intel_lvds_init()
837 u32 lvds; in intel_lvds_init() local
841 /* Skip init on machines we know falsely report LVDS */ in intel_lvds_init()
843 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, in intel_lvds_init()
844 "Useless DMI match. Internal LVDS support disabled by VBT\n"); in intel_lvds_init()
848 if (!dev_priv->vbt.int_lvds_support) { in intel_lvds_init()
849 drm_dbg_kms(&dev_priv->drm, in intel_lvds_init()
850 "Internal LVDS support disabled by VBT\n"); in intel_lvds_init()
857 lvds_reg = LVDS; in intel_lvds_init()
859 lvds = intel_de_read(dev_priv, lvds_reg); in intel_lvds_init()
862 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()
868 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()
869 drm_dbg_kms(&dev_priv->drm, in intel_lvds_init()
870 "LVDS is not present in VBT\n"); in intel_lvds_init()
873 drm_dbg_kms(&dev_priv->drm, in intel_lvds_init()
874 "LVDS is not present in VBT, but enabled anyway\n"); in intel_lvds_init()
887 lvds_encoder->attached_connector = intel_connector; in intel_lvds_init()
889 intel_encoder = &lvds_encoder->base; in intel_lvds_init()
890 encoder = &intel_encoder->base; in intel_lvds_init()
891 connector = &intel_connector->base; in intel_lvds_init()
892 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, in intel_lvds_init()
895 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, in intel_lvds_init()
896 DRM_MODE_ENCODER_LVDS, "LVDS"); in intel_lvds_init()
898 intel_encoder->enable = intel_enable_lvds; in intel_lvds_init()
899 intel_encoder->pre_enable = intel_pre_enable_lvds; in intel_lvds_init()
900 intel_encoder->compute_config = intel_lvds_compute_config; in intel_lvds_init()
902 intel_encoder->disable = pch_disable_lvds; in intel_lvds_init()
903 intel_encoder->post_disable = pch_post_disable_lvds; in intel_lvds_init()
905 intel_encoder->disable = gmch_disable_lvds; in intel_lvds_init()
907 intel_encoder->get_hw_state = intel_lvds_get_hw_state; in intel_lvds_init()
908 intel_encoder->get_config = intel_lvds_get_config; in intel_lvds_init()
909 intel_encoder->update_pipe = intel_panel_update_backlight; in intel_lvds_init()
910 intel_encoder->shutdown = intel_lvds_shutdown; in intel_lvds_init()
911 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_lvds_init()
915 intel_encoder->type = INTEL_OUTPUT_LVDS; in intel_lvds_init()
916 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; in intel_lvds_init()
917 intel_encoder->port = PORT_NONE; in intel_lvds_init()
918 intel_encoder->cloneable = 0; in intel_lvds_init()
920 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
922 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
925 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in intel_lvds_init()
926 connector->interlace_allowed = false; in intel_lvds_init()
927 connector->doublescan_allowed = false; in intel_lvds_init()
929 lvds_encoder->reg = lvds_reg; in intel_lvds_init()
936 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; in intel_lvds_init()
938 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); in intel_lvds_init()
939 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()
942 * LVDS discovery: in intel_lvds_init()
945 * 3) check to see if LVDS is already on in intel_lvds_init()
946 * if none of the above, no panel in intel_lvds_init()
950 * Attempt to get the fixed panel mode from DDC. Assume that the in intel_lvds_init()
953 mutex_lock(&dev->mode_config.mutex); in intel_lvds_init()
966 edid = ERR_PTR(-EINVAL); in intel_lvds_init()
969 edid = ERR_PTR(-ENOENT); in intel_lvds_init()
971 intel_connector->edid = edid; in intel_lvds_init()
983 * If we didn't get EDID, try checking if the panel is already turned in intel_lvds_init()
989 drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: "); in intel_lvds_init()
991 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; in intel_lvds_init()
999 mutex_unlock(&dev->mode_config.mutex); in intel_lvds_init()
1001 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); in intel_lvds_init()
1004 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); in intel_lvds_init()
1005 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", in intel_lvds_init()
1006 lvds_encoder->is_dual_link ? "dual" : "single"); in intel_lvds_init()
1008 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
1013 mutex_unlock(&dev->mode_config.mutex); in intel_lvds_init()
1015 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); in intel_lvds_init()