44  * occurrence until the next modeset on a given pipe.
47  * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
59 	enum pipe pipe;  in ivb_can_enable_err_int()  local
63 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
64 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in ivb_can_enable_err_int()
76 	enum pipe pipe;  in cpt_can_enable_serr_int()  local
81 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
82 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in cpt_can_enable_serr_int()
94 	i915_reg_t reg = PIPESTAT(crtc->pipe);  in i9xx_check_fifo_underruns()
102 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
106 	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
107 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
111 					     enum pipe pipe,  in i9xx_set_fifo_underrun_reporting()  argument
115 	i915_reg_t reg = PIPESTAT(pipe);  in i9xx_set_fifo_underrun_reporting()
120 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_set_fifo_underrun_reporting()
127 			drm_err(&dev_priv->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
128 				pipe_name(pipe));  in i9xx_set_fifo_underrun_reporting()
133 					    enum pipe pipe, bool enable)  in ilk_set_fifo_underrun_reporting()  argument
136 	u32 bit = (pipe == PIPE_A) ?  in ilk_set_fifo_underrun_reporting()
148 	enum pipe pipe = crtc->pipe;  in ivb_check_fifo_underruns()  local
153 	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)  in ivb_check_fifo_underruns()
156 	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_check_fifo_underruns()
159 	trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in ivb_check_fifo_underruns()
160 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
164 					    enum pipe pipe, bool enable,  in ivb_set_fifo_underrun_reporting()  argument
170 			       ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_set_fifo_underrun_reporting()
180 		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivb_set_fifo_underrun_reporting()
182 				"uncleared fifo underrun on pipe %c\n",  in ivb_set_fifo_underrun_reporting()
183 				pipe_name(pipe));  in ivb_set_fifo_underrun_reporting()
202 					    enum pipe pipe, bool enable)  in bdw_set_fifo_underrun_reporting()  argument
209 			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),  in bdw_set_fifo_underrun_reporting()
212 		bdw_enable_pipe_irq(dev_priv, pipe, mask);  in bdw_set_fifo_underrun_reporting()
214 		bdw_disable_pipe_irq(dev_priv, pipe, mask);  in bdw_set_fifo_underrun_reporting()
219 					    enum pipe pch_transcoder,  in ibx_set_fifo_underrun_reporting()
235 	enum pipe pch_transcoder = crtc->pipe;  in cpt_check_pch_fifo_underruns()
253 					    enum pipe pch_transcoder,  in cpt_set_fifo_underrun_reporting()
279 						    enum pipe pipe, bool enable)  in __intel_set_cpu_fifo_underrun_reporting()  argument
282 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
291 		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
293 		ilk_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
295 		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
297 		bdw_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
305  * @pipe: (CPU) pipe to set state for
308  * This function sets the fifo underrun state for @pipe. It is used in the
310  * expected when disabling or enabling the pipe.
312  * Notice that on some platforms disabling underrun reports for one pipe
313  * disables for all due to shared interrupts. Actual reporting is still per-pipe
319 					   enum pipe pipe, bool enable)  in intel_set_cpu_fifo_underrun_reporting()  argument
325 	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,  in intel_set_cpu_fifo_underrun_reporting()
335  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
347 					   enum pipe pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
356 	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT  in intel_set_pch_fifo_underrun_reporting()
358 	 * pch transcoder -> pipe lookups from interrupt code simply store the  in intel_set_pch_fifo_underrun_reporting()
385  * @pipe: (CPU) pipe to set state for
392 					 enum pipe pipe)  in intel_cpu_fifo_underrun_irq_handler()  argument
394 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
418 		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &  in intel_cpu_fifo_underrun_irq_handler()
420 		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);  in intel_cpu_fifo_underrun_irq_handler()
423 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
424 		trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
427 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",  in intel_cpu_fifo_underrun_irq_handler()
428 				pipe_name(pipe),  in intel_cpu_fifo_underrun_irq_handler()
434 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
443  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
450 					 enum pipe pch_transcoder)  in intel_pch_fifo_underrun_irq_handler()