73 	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {  in intel_atomic_duplicate_dpll_state()
74 		struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];  in intel_atomic_duplicate_dpll_state()
109 	return &dev_priv->dpll.shared_dplls[id];  in intel_get_shared_dpll_by_id()
124 	long pll_idx = pll - dev_priv->dpll.shared_dplls;  in intel_get_shared_dpll_id()
128 			pll_idx >= dev_priv->dpll.num_shared_dpll))  in intel_get_shared_dpll_id()
203 	mutex_lock(&dev_priv->dpll.lock);  in intel_prepare_shared_dpll()
212 	mutex_unlock(&dev_priv->dpll.lock);  in intel_prepare_shared_dpll()
232 	mutex_lock(&dev_priv->dpll.lock);  in intel_enable_shared_dpll()
258 	mutex_unlock(&dev_priv->dpll.lock);  in intel_enable_shared_dpll()
281 	mutex_lock(&dev_priv->dpll.lock);  in intel_disable_shared_dpll()
304 	mutex_unlock(&dev_priv->dpll.lock);  in intel_disable_shared_dpll()
323 		pll = &dev_priv->dpll.shared_dplls[i];  in intel_find_shared_dpll()
423 	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {  in intel_shared_dpll_swap_state()
425 			&dev_priv->dpll.shared_dplls[i];  in intel_shared_dpll_swap_state()
445 	hw_state->dpll = val;  in ibx_pch_dpll_get_hw_state()
484 	intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);  in ibx_pch_dpll_enable()
495 	intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);  in ibx_pch_dpll_enable()
523 		pll = &dev_priv->dpll.shared_dplls[i];  in ibx_get_dpll()
554 		    hw_state->dpll,  in ibx_dump_hw_state()
932 			refclk = dev_priv->dpll.ref_clks.nssc;  in hsw_ddi_wrpll_get_freq()
942 		refclk = dev_priv->dpll.ref_clks.ssc;  in hsw_ddi_wrpll_get_freq()
1090 	i915->dpll.ref_clks.ssc = 135000;  in hsw_update_dpll_ref_clks()
1093 		i915->dpll.ref_clks.nssc = 24000;  in hsw_update_dpll_ref_clks()
1095 		i915->dpll.ref_clks.nssc = 135000;  in hsw_update_dpll_ref_clks()
1586 				     i915->dpll.ref_clks.nssc,  in skl_ddi_hdmi_pll_dividers()
1613 	int ref_clock = i915->dpll.ref_clks.nssc;  in skl_ddi_wrpll_get_freq()
1820 	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;  in skl_update_dpll_ref_clks()
2117 	struct dpll best_clock;  in bxt_ddi_hdmi_pll_dividers()
2255 	struct dpll clock;  in bxt_ddi_pll_get_freq()
2265 	return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);  in bxt_ddi_pll_get_freq()
2303 	i915->dpll.ref_clks.ssc = 100000;  in bxt_update_dpll_ref_clks()
2304 	i915->dpll.ref_clks.nssc = 100000;  in bxt_update_dpll_ref_clks()
2446 		 i915->dpll.ref_clks.nssc == 38400;  in ehl_combo_pll_div_frac_wa_needed()
2540 		dev_priv->dpll.ref_clks.nssc == 24000 ?  in icl_calc_dp_combo_pll()
2563 		switch (dev_priv->dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
2565 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
2576 		switch (dev_priv->dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
2578 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
2608 	int ref_clock = i915->dpll.ref_clks.nssc;  in icl_wrpll_ref_clock()
2834 	int refclk_khz = dev_priv->dpll.ref_clks.nssc;  in icl_calc_mg_pll_state()
3042 	ref_clock = dev_priv->dpll.ref_clks.nssc;  in icl_ddi_mg_pll_get_freq()
3387 	if (dev_priv->dpll.ref_clks.nssc == 38400) {  in mg_pll_get_hw_state()
3905 	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;  in icl_update_dpll_ref_clks()
4123 		dev_priv->dpll.num_shared_dpll = 0;  in intel_shared_dpll_init()
4131 		dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];  in intel_shared_dpll_init()
4134 	dev_priv->dpll.mgr = dpll_mgr;  in intel_shared_dpll_init()
4135 	dev_priv->dpll.num_shared_dpll = i;  in intel_shared_dpll_init()
4136 	mutex_init(&dev_priv->dpll.lock);  in intel_shared_dpll_init()
4138 	BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);  in intel_shared_dpll_init()
4165 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;  in intel_reserve_shared_dplls()
4188 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;  in intel_release_shared_dplls()
4217 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;  in intel_update_active_dpll()
4288 	if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)  in intel_dpll_update_ref_clks()
4289 		i915->dpll.mgr->update_ref_clks(i915);  in intel_dpll_update_ref_clks()
4296 	for (i = 0; i < i915->dpll.num_shared_dpll; i++)  in intel_dpll_readout_hw_state()
4297 		readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);  in intel_dpll_readout_hw_state()
4323 	for (i = 0; i < i915->dpll.num_shared_dpll; i++)  in intel_dpll_sanitize_state()
4324 		sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);  in intel_dpll_sanitize_state()
4337 	if (dev_priv->dpll.mgr) {  in intel_dpll_dump_hw_state()
4338 		dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);  in intel_dpll_dump_hw_state()
4346 			    hw_state->dpll,  in intel_dpll_dump_hw_state()