Lines Matching +full:ssc +full:- +full:range
1 // SPDX-License-Identifier: MIT
179 * the range value for them is (actual_value - 2).
292 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
293 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
297 * divided-down version of it.
302 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
303 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
304 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
306 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
307 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
309 return clock->dot; in pnv_calc_dpll_params()
314 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
319 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
320 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
321 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) in i9xx_calc_dpll_params()
323 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
324 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
326 return clock->dot; in i9xx_calc_dpll_params()
331 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
332 clock->p = clock->p1 * clock->p2; in vlv_calc_dpll_params()
333 if (WARN_ON(clock->n == 0 || clock->p == 0)) in vlv_calc_dpll_params()
335 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
336 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
338 return clock->dot / 5; in vlv_calc_dpll_params()
343 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
344 clock->p = clock->p1 * clock->p2; in chv_calc_dpll_params()
345 if (WARN_ON(clock->n == 0 || clock->p == 0)) in chv_calc_dpll_params()
347 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
348 clock->n << 22); in chv_calc_dpll_params()
349 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
351 return clock->dot / 5; in chv_calc_dpll_params()
362 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
364 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
366 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
368 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
372 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
376 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
378 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
382 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
385 * connector, etc., rather than just a single range. in intel_pll_is_valid()
387 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
398 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
402 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
407 return limit->p2.p2_fast; in i9xx_select_p2_div()
409 return limit->p2.p2_slow; in i9xx_select_p2_div()
411 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
412 return limit->p2.p2_slow; in i9xx_select_p2_div()
414 return limit->p2.p2_fast; in i9xx_select_p2_div()
434 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
442 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
444 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
445 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
448 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
449 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
450 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
451 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
460 clock.p != match_clock->p) in i9xx_find_best_dpll()
463 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
492 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
500 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
502 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
503 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
504 for (clock.n = limit->n.min; in pnv_find_best_dpll()
505 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
506 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
507 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
516 clock.p != match_clock->p) in pnv_find_best_dpll()
519 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
548 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
559 max_n = limit->n.max; in g4x_find_best_dpll()
561 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
563 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
564 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
565 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
566 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
567 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
568 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
577 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
608 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
615 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
622 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
643 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
647 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
655 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
656 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
657 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
658 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
661 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
703 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
721 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
722 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
723 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
724 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
762 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
768 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_update_pll_dividers()
779 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
783 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
788 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
792 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
794 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
804 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
817 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
830 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
834 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
836 switch (clock->p2) { in i9xx_compute_dpll()
853 if (crtc_state->sdvo_tv_clock) in i9xx_compute_dpll()
862 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
865 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
867 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
875 struct drm_device *dev = crtc->base.dev; in i8xx_compute_dpll()
878 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
885 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
887 if (clock->p1 == 2) in i8xx_compute_dpll()
890 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
891 if (clock->p2 == 4) in i8xx_compute_dpll()
901 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
918 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_compute_clock()
926 to_intel_atomic_state(crtc_state->uapi.state); in hsw_crtc_compute_clock()
935 drm_dbg_kms(&dev_priv->drm, in hsw_crtc_compute_clock()
937 pipe_name(crtc->pipe)); in hsw_crtc_compute_clock()
938 return -EINVAL; in hsw_crtc_compute_clock()
947 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ilk_needs_fb_cb_tune()
955 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_dpll()
963 dev_priv->vbt.lvds_ssc_freq == 100000) || in ilk_compute_dpll()
967 } else if (crtc_state->sdvo_tv_clock) { in ilk_compute_dpll()
971 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ilk_compute_dpll()
973 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ilk_compute_dpll()
979 if (reduced_clock->m < factor * reduced_clock->n) in ilk_compute_dpll()
992 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1014 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
1021 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1023 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1025 switch (crtc_state->dpll.p2) { in ilk_compute_dpll()
1048 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1049 crtc_state->dpll_hw_state.fp0 = fp; in ilk_compute_dpll()
1050 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_compute_dpll()
1056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_compute_clock()
1058 to_intel_atomic_state(crtc_state->uapi.state); in ilk_crtc_compute_clock()
1062 memset(&crtc_state->dpll_hw_state, 0, in ilk_crtc_compute_clock()
1063 sizeof(crtc_state->dpll_hw_state)); in ilk_crtc_compute_clock()
1066 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1071 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1072 "using SSC reference clock of %d kHz\n", in ilk_crtc_compute_clock()
1073 dev_priv->vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1074 refclk = dev_priv->vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1092 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1093 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1094 refclk, NULL, &crtc_state->dpll)) { in ilk_crtc_compute_clock()
1095 drm_err(&dev_priv->drm, in ilk_crtc_compute_clock()
1097 return -EINVAL; in ilk_crtc_compute_clock()
1103 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1105 pipe_name(crtc->pipe)); in ilk_crtc_compute_clock()
1106 return -EINVAL; in ilk_crtc_compute_clock()
1115 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1117 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1118 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1122 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1125 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
1126 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
1132 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1134 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1135 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1139 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1141 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
1142 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
1150 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in chv_crtc_compute_clock()
1152 memset(&crtc_state->dpll_hw_state, 0, in chv_crtc_compute_clock()
1153 sizeof(crtc_state->dpll_hw_state)); in chv_crtc_compute_clock()
1155 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1156 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1157 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
1158 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); in chv_crtc_compute_clock()
1159 return -EINVAL; in chv_crtc_compute_clock()
1172 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in vlv_crtc_compute_clock()
1174 memset(&crtc_state->dpll_hw_state, 0, in vlv_crtc_compute_clock()
1175 sizeof(crtc_state->dpll_hw_state)); in vlv_crtc_compute_clock()
1177 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1178 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1179 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1180 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); in vlv_crtc_compute_clock()
1181 return -EINVAL; in vlv_crtc_compute_clock()
1192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_crtc_compute_clock()
1196 memset(&crtc_state->dpll_hw_state, 0, in g4x_crtc_compute_clock()
1197 sizeof(crtc_state->dpll_hw_state)); in g4x_crtc_compute_clock()
1201 refclk = dev_priv->vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1202 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1203 "using SSC reference clock of %d kHz\n", in g4x_crtc_compute_clock()
1221 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1222 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1223 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
1224 drm_err(&dev_priv->drm, in g4x_crtc_compute_clock()
1226 return -EINVAL; in g4x_crtc_compute_clock()
1237 struct drm_device *dev = crtc->base.dev; in pnv_crtc_compute_clock()
1242 memset(&crtc_state->dpll_hw_state, 0, in pnv_crtc_compute_clock()
1243 sizeof(crtc_state->dpll_hw_state)); in pnv_crtc_compute_clock()
1247 refclk = dev_priv->vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1248 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1249 "using SSC reference clock of %d kHz\n", in pnv_crtc_compute_clock()
1258 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1259 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1260 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
1261 drm_err(&dev_priv->drm, in pnv_crtc_compute_clock()
1263 return -EINVAL; in pnv_crtc_compute_clock()
1274 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_compute_clock()
1279 memset(&crtc_state->dpll_hw_state, 0, in i9xx_crtc_compute_clock()
1280 sizeof(crtc_state->dpll_hw_state)); in i9xx_crtc_compute_clock()
1284 refclk = dev_priv->vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1285 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1286 "using SSC reference clock of %d kHz\n", in i9xx_crtc_compute_clock()
1295 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1296 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1297 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
1298 drm_err(&dev_priv->drm, in i9xx_crtc_compute_clock()
1300 return -EINVAL; in i9xx_crtc_compute_clock()
1311 struct drm_device *dev = crtc->base.dev; in i8xx_crtc_compute_clock()
1316 memset(&crtc_state->dpll_hw_state, 0, in i8xx_crtc_compute_clock()
1317 sizeof(crtc_state->dpll_hw_state)); in i8xx_crtc_compute_clock()
1321 refclk = dev_priv->vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1322 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1323 "using SSC reference clock of %d kHz\n", in i8xx_crtc_compute_clock()
1334 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1335 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1336 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
1337 drm_err(&dev_priv->drm, in i8xx_crtc_compute_clock()
1339 return -EINVAL; in i8xx_crtc_compute_clock()
1351 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; in intel_dpll_init_clock_hook()
1353 dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock; in intel_dpll_init_clock_hook()
1355 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; in intel_dpll_init_clock_hook()
1357 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; in intel_dpll_init_clock_hook()
1359 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; in intel_dpll_init_clock_hook()
1361 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; in intel_dpll_init_clock_hook()
1363 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_dpll_init_clock_hook()
1365 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; in intel_dpll_init_clock_hook()
1379 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1380 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1381 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1384 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1388 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1403 intel_de_write(dev_priv, DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1404 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1454 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
1455 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1462 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
1469 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
1471 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); in vlv_enable_pll()
1476 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1480 pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
1489 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1512 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
1518 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
1519 enum pipe pipe = crtc->pipe; in chv_enable_pll()
1521 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); in chv_enable_pll()
1526 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1538 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1540 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1546 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
1551 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1559 struct drm_device *dev = crtc->base.dev; in vlv_prepare_pll()
1561 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1568 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
1571 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
1576 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
1577 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
1578 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
1579 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
1580 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
1617 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
1627 /* Use SSC source */ in vlv_prepare_pll()
1658 struct drm_device *dev = crtc->base.dev; in chv_prepare_pll()
1660 enum pipe pipe = crtc->pipe; in chv_prepare_pll()
1667 /* Enable Refclk and SSC */ in chv_prepare_pll()
1669 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
1672 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
1675 bestn = pipe_config->dpll.n; in chv_prepare_pll()
1676 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1677 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
1678 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
1679 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
1680 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
1681 vco = pipe_config->dpll.vco; in chv_prepare_pll()
1694 /* Feedback post-divider - m2 */ in chv_prepare_pll()
1697 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
1761 * vlv_force_pll_on - forcibly enable just the PLL
1778 return -ENOMEM; in vlv_force_pll_on()
1780 pipe_config->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
1781 pipe_config->pixel_multiplier = 1; in vlv_force_pll_on()
1782 pipe_config->dpll = *dpll; in vlv_force_pll_on()
1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
1845 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
1852 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
1860 * vlv_force_pll_off - forcibly disable just the PLL