220 /* LVDS 100mhz refclk limits. */
300 int pnv_calc_dpll_params(int refclk, struct dpll *clock)  in pnv_calc_dpll_params()  argument
306 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in pnv_calc_dpll_params()
317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)  in i9xx_calc_dpll_params()  argument
323 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);  in i9xx_calc_dpll_params()
329 int vlv_calc_dpll_params(int refclk, struct dpll *clock)  in vlv_calc_dpll_params()  argument
335 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in vlv_calc_dpll_params()
341 int chv_calc_dpll_params(int refclk, struct dpll *clock)  in chv_calc_dpll_params()  argument
347 	clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),  in chv_calc_dpll_params()
355  * Returns whether the given set of divisors are valid for a given refclk with
420  * refclk, or FALSE.  The returned values represent the clock equation:
431 		    int target, int refclk, struct dpll *match_clock,  in i9xx_find_best_dpll()  argument
454 					i9xx_calc_dpll_params(refclk, &clock);  in i9xx_find_best_dpll()
478  * refclk, or FALSE.  The returned values represent the clock equation:
489 		   int target, int refclk, struct dpll *match_clock,  in pnv_find_best_dpll()  argument
510 					pnv_calc_dpll_params(refclk, &clock);  in pnv_find_best_dpll()
534  * refclk, or FALSE.  The returned values represent the clock equation:
545 		   int target, int refclk, struct dpll *match_clock,  in g4x_find_best_dpll()  argument
571 					i9xx_calc_dpll_params(refclk, &clock);  in g4x_find_best_dpll()
633  * refclk, or FALSE.  The returned values represent the clock equation:
639 		   int target, int refclk, struct dpll *match_clock,  in vlv_find_best_dpll()  argument
647 	int max_n = min(limit->n.max, refclk / 19200);  in vlv_find_best_dpll()
665 								     refclk * clock.m1);  in vlv_find_best_dpll()
667 					vlv_calc_dpll_params(refclk, &clock);  in vlv_find_best_dpll()
693  * refclk, or FALSE.  The returned values represent the clock equation:
699 		   int target, int refclk, struct dpll *match_clock,  in chv_find_best_dpll()  argument
714 	 * set to 2.  If requires to support 200Mhz refclk, we need to  in chv_find_best_dpll()
730 						   refclk * clock.m1);  in chv_find_best_dpll()
737 			chv_calc_dpll_params(refclk, &clock);  in chv_find_best_dpll()
758 	int refclk = 100000;  in bxt_find_best_dpll()  local
762 				  crtc_state->port_clock, refclk,  in bxt_find_best_dpll()
1060 	int refclk = 120000;  in ilk_crtc_compute_clock()  local
1074 			refclk = dev_priv->vbt.lvds_ssc_freq;  in ilk_crtc_compute_clock()
1078 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1083 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1094 				refclk, NULL, &crtc_state->dpll)) {  in ilk_crtc_compute_clock()
1148 	int refclk = 100000;  in chv_crtc_compute_clock()  local
1157 				refclk, NULL, &crtc_state->dpll)) {  in chv_crtc_compute_clock()
1170 	int refclk = 100000;  in vlv_crtc_compute_clock()  local
1179 				refclk, NULL, &crtc_state->dpll)) {  in vlv_crtc_compute_clock()
1194 	int refclk = 96000;  in g4x_crtc_compute_clock()  local
1201 			refclk = dev_priv->vbt.lvds_ssc_freq;  in g4x_crtc_compute_clock()
1204 				    refclk);  in g4x_crtc_compute_clock()
1223 				refclk, NULL, &crtc_state->dpll)) {  in g4x_crtc_compute_clock()
1240 	int refclk = 96000;  in pnv_crtc_compute_clock()  local
1247 			refclk = dev_priv->vbt.lvds_ssc_freq;  in pnv_crtc_compute_clock()
1250 				    refclk);  in pnv_crtc_compute_clock()
1260 				refclk, NULL, &crtc_state->dpll)) {  in pnv_crtc_compute_clock()
1277 	int refclk = 96000;  in i9xx_crtc_compute_clock()  local
1284 			refclk = dev_priv->vbt.lvds_ssc_freq;  in i9xx_crtc_compute_clock()
1287 				    refclk);  in i9xx_crtc_compute_clock()
1297 				 refclk, NULL, &crtc_state->dpll)) {  in i9xx_crtc_compute_clock()
1314 	int refclk = 48000;  in i8xx_crtc_compute_clock()  local
1321 			refclk = dev_priv->vbt.lvds_ssc_freq;  in i8xx_crtc_compute_clock()
1324 				    refclk);  in i8xx_crtc_compute_clock()
1336 				 refclk, NULL, &crtc_state->dpll)) {  in i8xx_crtc_compute_clock()
1566 	/* Enable Refclk */  in vlv_prepare_pll()
1667 	/* Enable Refclk and SSC */  in chv_prepare_pll()
1697 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()