19 	} dot, vco, n, m, m1, m2, p, p1;  member
31 	.m1 = { .min = 18, .max = 26 },
44 	.m1 = { .min = 18, .max = 26 },
57 	.m1 = { .min = 18, .max = 26 },
70 	.m1 = { .min = 8, .max = 18 },
83 	.m1 = { .min = 8, .max = 18 },
97 	.m1 = { .min = 17, .max = 23 },
112 	.m1 = { .min = 16, .max = 23 },
125 	.m1 = { .min = 17, .max = 23 },
139 	.m1 = { .min = 17, .max = 23 },
155 	.m1 = { .min = 0, .max = 0 },
168 	.m1 = { .min = 0, .max = 0 },
178  * We calculate clock using (register_value + 2) for N/M1/M2, so here
186 	.m1 = { .min = 12, .max = 22 },
199 	.m1 = { .min = 12, .max = 22 },
212 	.m1 = { .min = 12, .max = 22 },
226 	.m1 = { .min = 12, .max = 22 },
239 	.m1 = { .min = 12, .max = 22 },
257 	.m1 = { .min = 2, .max = 3 },
273 	.m1 = { .min = 2, .max = 2 },
284 	.m1 = { .min = 2, .max = 2 },
299 /* m1 is reserved as 0 in Pineview, n is a ring counter */
314 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
331 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
343 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
368 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
372 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
421  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
442 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
443 	     clock.m1++) {  in i9xx_find_best_dpll()
446 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
479  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
500 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
501 	     clock.m1++) {  in pnv_find_best_dpll()
535  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
562 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
563 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
564 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
634  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
660 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
661 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
665 								     refclk * clock.m1);  in vlv_find_best_dpll()
694  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 	 * Based on hardware doc, the n always set to 1, and m1 always  in chv_find_best_dpll()
718 	clock.m1 = 2;  in chv_find_best_dpll()
730 						   refclk * clock.m1);  in chv_find_best_dpll()
732 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
1577 	bestm1 = pipe_config->dpll.m1;  in vlv_prepare_pll()
1677 	bestm1 = pipe_config->dpll.m1;  in chv_prepare_pll()
1697 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()