Lines Matching full:well
193 "Use count on power well %s is already zero", in intel_power_well_put()
247 * threads can't disable the power well while the caller tries to read a few
269 * Starting with Haswell, we have a "Power Down Well" that can be turned off
270 * when not needed anymore. We have 4 registers that can request the power well
362 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", in hsw_wait_for_power_well_enable()
397 * - a KVMR request on any power well via the KVMR request register in hsw_wait_for_power_well_disable()
438 * before enabling the power well and PW1/PG1's own fuse in hsw_power_well_enable()
694 * We should only use the power well if we explicitly asked the hardware to
735 "Power well 2 on.\n"); in assert_can_enable_dc9()
990 * the first power well and hope the WARN gets reported so we can fix in lookup_power_well()
994 "Power well %d not defined for this platform\n", in lookup_power_well()
1004 * This function set the "DC off" power well target_dc_state,
1005 * based upon this target_dc_stste, "DC off" power well will
1029 * If DC off power well is disabled, need to enable and disable the in intel_display_power_set_target_dc_state()
1030 * DC off power well to effect target DC state. in intel_display_power_set_target_dc_state()
1318 "timeout setting power well state %08x (%08x)\n", in vlv_set_power_well()
1542 * reset (ie. the power well has been disabled at in assert_chv_phy_status()
1743 * reset (ie. the power well has been disabled at in assert_chv_phy_powergate()
1917 "timeout setting power well state %08x (%08x)\n", in chv_set_pipe_power_well()
2228 * power well disabling. in release_async_put_domains()
2978 * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
2989 * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
3098 * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
3361 * Pipe A power well is the new disp2d well. Pipe B and C
3362 * power wells don't actually exist. Pipe A power well is
3410 .name = "power well 1",
3423 .name = "MISC IO power well",
3441 .name = "power well 2",
3454 .name = "DDI A/E IO power well",
3464 .name = "DDI B IO power well",
3474 .name = "DDI C IO power well",
3484 .name = "DDI D IO power well",
3504 .name = "power well 1",
3523 .name = "power well 2",
3564 .name = "power well 1",
3583 .name = "power well 2",
3653 .name = "DDI A IO power well",
3663 .name = "DDI B IO power well",
3673 .name = "DDI C IO power well",
3712 .name = "power well 1",
3731 .name = "power well 2",
3742 .name = "power well 3",
3923 .name = "power well 4",
4030 .name = "power well 1",
4049 .name = "power well 2",
4060 .name = "power well 3",
4331 .name = "power well 4",
4343 .name = "power well 5",
4365 .name = "power well 1",
4384 .name = "power well 3",
4397 .name = "power well 4",
4499 .name = "power well 1",
4518 .name = "power well 2",
4529 .name = "power well 3",
4624 .name = "power well 4",
4636 .name = "power well 5",
4658 .name = "power well 1",
4677 .name = "power well 2",
4689 .name = "power well A",
4701 .name = "power well B",
4713 .name = "power well C",
4725 .name = "power well D",
5290 * expect us to program the abox_ctl0 register as well, even though in icl_mbus_init()
5330 "Display power well on\n"); in assert_can_disable_lcpll()
5495 * well is disabled and most interrupts are disabled, and these are also
5571 struct i915_power_well *well; in skl_display_core_init() local
5584 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_init()
5585 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
5587 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
5588 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
5603 struct i915_power_well *well; in skl_display_core_uninit() local
5620 * BSpec says to keep the MISC IO power well enabled here, only in skl_display_core_uninit()
5621 * remove our request for power well 1. in skl_display_core_uninit()
5622 * Note that even though the driver's request is removed power well 1 in skl_display_core_uninit()
5625 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_uninit()
5626 intel_power_well_disable(dev_priv, well); in skl_display_core_uninit()
5636 struct i915_power_well *well; in bxt_display_core_init() local
5654 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_init()
5655 intel_power_well_enable(dev_priv, well); in bxt_display_core_init()
5670 struct i915_power_well *well; in bxt_display_core_uninit() local
5685 * Note that even though the driver's request is removed power well 1 in bxt_display_core_uninit()
5690 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_uninit()
5691 intel_power_well_disable(dev_priv, well); in bxt_display_core_uninit()
5778 struct i915_power_well *well; in icl_display_core_init() local
5799 * 3. Enable Power Well 1 (PG1). in icl_display_core_init()
5803 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in icl_display_core_init()
5804 intel_power_well_enable(dev_priv, well); in icl_display_core_init()
5845 struct i915_power_well *well; in icl_display_core_uninit() local
5861 * 4. Disable Power Well 1 (PG1). in icl_display_core_uninit()
5866 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in icl_display_core_uninit()
5867 intel_power_well_disable(dev_priv, well); in icl_display_core_uninit()
5885 * power well state and lane status to reconstruct the in chv_phy_control_init()
6031 * power well must match its HW enabled state, see
6105 /* Remove the refcount we took to keep power well support disabled. */ in intel_power_domains_driver_remove()
6114 /* Keep the power well enabled, but cancel its rpm wakeref. */ in intel_power_domains_driver_remove()
6193 * Even if power well support was disabled we still want to disable in intel_power_domains_suspend()
6263 * Verify if the reference count of each power well matches its HW enabled
6289 "power well %s state mismatch (refcount %d/enabled %d)", in intel_power_domains_verify_state()
6299 "power well %s refcount/domain refcount mismatch " in intel_power_domains_verify_state()