4405 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
4452 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
4461 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()  local
4464 	drm_mode_copy(pipe_mode, adjusted_mode);  in intel_crtc_readout_derived_state()
4471 		pipe_mode->crtc_hdisplay /= 2;  in intel_crtc_readout_derived_state()
4472 		pipe_mode->crtc_hblank_start /= 2;  in intel_crtc_readout_derived_state()
4473 		pipe_mode->crtc_hblank_end /= 2;  in intel_crtc_readout_derived_state()
4474 		pipe_mode->crtc_hsync_start /= 2;  in intel_crtc_readout_derived_state()
4475 		pipe_mode->crtc_hsync_end /= 2;  in intel_crtc_readout_derived_state()
4476 		pipe_mode->crtc_htotal /= 2;  in intel_crtc_readout_derived_state()
4477 		pipe_mode->crtc_clock /= 2;  in intel_crtc_readout_derived_state()
4490 		pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;  in intel_crtc_readout_derived_state()
4491 		pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;  in intel_crtc_readout_derived_state()
4492 		pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;  in intel_crtc_readout_derived_state()
4493 		pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;  in intel_crtc_readout_derived_state()
4494 		pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;  in intel_crtc_readout_derived_state()
4495 		pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;  in intel_crtc_readout_derived_state()
4496 		pipe_mode->crtc_clock *= n;  in intel_crtc_readout_derived_state()
4498 		intel_mode_from_crtc_timings(pipe_mode, pipe_mode);  in intel_crtc_readout_derived_state()
4499 		intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);  in intel_crtc_readout_derived_state()
4501 		intel_mode_from_crtc_timings(pipe_mode, pipe_mode);  in intel_crtc_readout_derived_state()
4524 	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;  in intel_crtc_compute_config()  local
4527 	drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);  in intel_crtc_compute_config()
4531 		pipe_mode->crtc_clock /= 2;  in intel_crtc_compute_config()
4532 		pipe_mode->crtc_hdisplay /= 2;  in intel_crtc_compute_config()
4533 		pipe_mode->crtc_hblank_start /= 2;  in intel_crtc_compute_config()
4534 		pipe_mode->crtc_hblank_end /= 2;  in intel_crtc_compute_config()
4535 		pipe_mode->crtc_hsync_start /= 2;  in intel_crtc_compute_config()
4536 		pipe_mode->crtc_hsync_end /= 2;  in intel_crtc_compute_config()
4537 		pipe_mode->crtc_htotal /= 2;  in intel_crtc_compute_config()
4545 		pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;  in intel_crtc_compute_config()
4546 		pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;  in intel_crtc_compute_config()
4547 		pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;  in intel_crtc_compute_config()
4548 		pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;  in intel_crtc_compute_config()
4549 		pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;  in intel_crtc_compute_config()
4550 		pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;  in intel_crtc_compute_config()
4551 		pipe_mode->crtc_clock *= n;  in intel_crtc_compute_config()
4554 	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);  in intel_crtc_compute_config()
4564 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_config()
4570 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_config()
4573 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_config()
4603 	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)  in intel_crtc_compute_config()
7275 	const struct drm_display_mode *pipe_mode =  in hsw_linetime_wm()  local
7276 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
7282 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
7283 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
7291 	const struct drm_display_mode *pipe_mode =  in hsw_ips_linetime_wm()  local
7292 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
7298 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
7308 	const struct drm_display_mode *pipe_mode =  in skl_linetime_wm()  local
7309 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
7315 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
7798 	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);  in intel_dump_pipe_config()
7799 	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);  in intel_dump_pipe_config()
8008 	crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;  in copy_bigjoiner_crtc_state()
8619 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);  in intel_pipe_config_compare()
8620 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);  in intel_pipe_config_compare()
8621 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);  in intel_pipe_config_compare()
8622 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);  in intel_pipe_config_compare()
8623 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);  in intel_pipe_config_compare()
8624 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);  in intel_pipe_config_compare()
8626 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);  in intel_pipe_config_compare()
8627 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);  in intel_pipe_config_compare()
8628 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);  in intel_pipe_config_compare()
8629 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);  in intel_pipe_config_compare()
8630 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);  in intel_pipe_config_compare()
8631 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);  in intel_pipe_config_compare()
8776 		PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);  in intel_pipe_config_compare()