Lines Matching refs:cdclk_state
4175 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic() local
4243 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic()
4244 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic()
4245 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()
4378 const struct intel_cdclk_state *cdclk_state; in hsw_compute_ips_config() local
4380 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_ips_config()
4381 if (IS_ERR(cdclk_state)) in hsw_compute_ips_config()
4382 return PTR_ERR(cdclk_state); in hsw_compute_ips_config()
4385 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_compute_ips_config()
7289 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument
7299 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
7332 const struct intel_cdclk_state *cdclk_state; in hsw_compute_linetime_wm() local
7342 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_linetime_wm()
7343 if (IS_ERR(cdclk_state)) in hsw_compute_linetime_wm()
7344 return PTR_ERR(cdclk_state); in hsw_compute_linetime_wm()
7347 cdclk_state); in hsw_compute_linetime_wm()
12144 struct intel_cdclk_state *cdclk_state; in intel_modeset_init_hw() local
12149 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); in intel_modeset_init_hw()
12153 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; in intel_modeset_init_hw()
13044 struct intel_cdclk_state *cdclk_state = in intel_modeset_readout_hw_state() local
13079 dev_priv->active_pipes = cdclk_state->active_pipes = in intel_modeset_readout_hw_state()
13220 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()
13221 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
13237 cdclk_state->min_cdclk[slave->pipe] = min_cdclk; in intel_modeset_readout_hw_state()
13238 cdclk_state->min_voltage_level[slave->pipe] = in intel_modeset_readout_hw_state()