2  * Copyright © 2006-2007 Intel Corporation
30 #include <linux/intel-iommu.h>
33 #include <linux/dma-resv.h>
137 #define i915_is_dpt(vm) ((vm)->is_dpt)
147 #define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
161 	gen8_pte_t __iomem *base = dpt->iomem;  in dpt_insert_page()
164 		     vm->pte_encode(addr, level, flags));  in dpt_insert_page()
173 	gen8_pte_t __iomem *base = dpt->iomem;  in dpt_insert_entries()
174 	const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);  in dpt_insert_entries()
184 	i = vma->node.start / I915_GTT_PAGE_SIZE;  in dpt_insert_entries()
185 	for_each_sgt_daddr(addr, sgt_iter, vma->pages)  in dpt_insert_entries()
200 	struct drm_i915_gem_object *obj = vma->obj;  in dpt_bind_vma()
205 	if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))  in dpt_bind_vma()
210 	vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);  in dpt_bind_vma()
212 	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;  in dpt_bind_vma()
217 	 * upgrade to both bound if we bind either to avoid double-binding.  in dpt_bind_vma()
219 	atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);  in dpt_bind_vma()
224 	vm->clear_range(vm, vma->node.start, vma->size);  in dpt_unbind_vma()
231 	i915_gem_object_put(dpt->obj);  in dpt_cleanup()
237 	struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;  in intel_dpt_create()
238 	struct drm_i915_private *i915 = to_i915(obj->dev);  in intel_dpt_create()
246 		size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);  in intel_dpt_create()
248 		size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);  in intel_dpt_create()
268 		return ERR_PTR(-ENOMEM);  in intel_dpt_create()
271 	vm = &dpt->vm;  in intel_dpt_create()
273 	vm->gt = &i915->gt;  in intel_dpt_create()
274 	vm->i915 = i915;  in intel_dpt_create()
275 	vm->dma = i915->drm.dev;  in intel_dpt_create()
276 	vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;  in intel_dpt_create()
277 	vm->is_dpt = true;  in intel_dpt_create()
281 	vm->insert_page = dpt_insert_page;  in intel_dpt_create()
282 	vm->clear_range = dpt_clear_range;  in intel_dpt_create()
283 	vm->insert_entries = dpt_insert_entries;  in intel_dpt_create()
284 	vm->cleanup = dpt_cleanup;  in intel_dpt_create()
286 	vm->vma_ops.bind_vma    = dpt_bind_vma;  in intel_dpt_create()
287 	vm->vma_ops.unbind_vma  = dpt_unbind_vma;  in intel_dpt_create()
288 	vm->vma_ops.set_pages   = ggtt_set_pages;  in intel_dpt_create()
289 	vm->vma_ops.clear_pages = clear_pages;  in intel_dpt_create()
291 	vm->pte_encode = gen8_ggtt_pte_encode;  in intel_dpt_create()
293 	dpt->obj = dpt_obj;  in intel_dpt_create()
295 	return &dpt->vm;  in intel_dpt_create()
302 	i915_vm_close(&dpt->vm);  in intel_dpt_destroy()
326 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=  in vlv_get_cck_clock()
340 	if (dev_priv->hpll_freq == 0)  in vlv_get_cck_clock_hpll()
341 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);  in vlv_get_cck_clock_hpll()
343 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);  in vlv_get_cck_clock_hpll()
355 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",  in intel_update_czclk()
358 	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",  in intel_update_czclk()
359 		dev_priv->czclk_freq);  in intel_update_czclk()
390 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
396 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
427 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in wait_for_pipe_scanline_moving()
428 	enum pipe pipe = crtc->pipe;  in wait_for_pipe_scanline_moving()
432 		drm_err(&dev_priv->drm,  in wait_for_pipe_scanline_moving()
450 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
451 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_wait_for_pipe_off()
454 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
460 			drm_WARN(&dev_priv->drm, 1,  in intel_wait_for_pipe_off()
467 /* Only for pre-ILK configs */
481 /* XXX: the dsi pll is shared between MIPI DSI ports */
507 		 * so pipe->transcoder cast is fine here.  in assert_fdi_tx()
576 	if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))  in assert_panel_unlocked()
612 		drm_WARN_ON(&dev_priv->drm,  in assert_panel_unlocked()
660 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
664 			plane->base.name, onoff(state), onoff(cur_state));  in assert_plane()
672 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in assert_planes_disabled()
675 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)  in assert_planes_disabled()
760 	switch (dig_port->base.port) {  in vlv_wait_port_ready()
780 		drm_WARN(&dev_priv->drm, 1,  in vlv_wait_port_ready()
782 			 dig_port->base.base.base.id, dig_port->base.base.name,  in vlv_wait_port_ready()
789 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_enable_pch_transcoder()
790 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_enable_pch_transcoder()
791 	enum pipe pipe = crtc->pipe;  in ilk_enable_pch_transcoder()
796 	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);  in ilk_enable_pch_transcoder()
812 		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in ilk_enable_pch_transcoder()
823 		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in ilk_enable_pch_transcoder()
850 		drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",  in ilk_enable_pch_transcoder()
868 	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in lpt_enable_pch_transcoder()
883 		drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");  in lpt_enable_pch_transcoder()
905 		drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",  in ilk_disable_pch_transcoder()
927 		drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");  in lpt_disable_pch_transcoder()
937 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_pch_transcoder()
942 		return crtc->pipe;  in intel_crtc_pch_transcoder()
947 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_pipe()
948 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_enable_pipe()
949 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_pipe()
950 	enum pipe pipe = crtc->pipe;  in intel_enable_pipe()
954 	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_pipe()
969 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_pipe()
979 	/* Wa_22012358565:adl-p */  in intel_enable_pipe()
988 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));  in intel_enable_pipe()
1008 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_pipe()
1009 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_disable_pipe()
1010 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_pipe()
1011 	enum pipe pipe = crtc->pipe;  in intel_disable_pipe()
1015 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_pipe()
1032 	if (old_crtc_state->double_wide)  in intel_disable_pipe()
1052 	return info->is_yuv &&  in intel_format_info_is_yuv_semiplanar()
1053 	       info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);  in intel_format_info_is_yuv_semiplanar()
1059 	struct drm_i915_private *dev_priv = to_i915(fb->dev);  in intel_tile_width_bytes()
1060 	unsigned int cpp = fb->format->cpp[color_plane];  in intel_tile_width_bytes()
1062 	switch (fb->modifier) {  in intel_tile_width_bytes()
1105 		MISSING_CASE(fb->modifier);  in intel_tile_width_bytes()
1124 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)  in intel_rotation_info_size()
1125 		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;  in intel_rotation_info_size()
1135 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)  in intel_remapped_info_size()
1136 		size += rem_info->plane[i].dst_stride * rem_info->plane[i].height;  in intel_remapped_info_size()
1162 	struct drm_i915_private *dev_priv = to_i915(fb->dev);  in intel_surf_alignment()
1173 		 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes  in intel_surf_alignment()
1177 			if (fb->modifier == DRM_FORMAT_MOD_LINEAR)  in intel_surf_alignment()
1186 	drm_WARN_ON(&dev_priv->drm, color_plane != 0);  in intel_surf_alignment()
1188 	switch (fb->modifier) {  in intel_surf_alignment()
1205 		MISSING_CASE(fb->modifier);  in intel_surf_alignment()
1212 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_uses_fence()
1213 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_plane_uses_fence()
1216 		(plane->has_fbc &&  in intel_plane_uses_fence()
1217 		 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);  in intel_plane_uses_fence()
1227 	struct drm_device *dev = fb->dev;  in intel_pin_fb_obj_dpt()
1235 		return ERR_PTR(-EINVAL);  in intel_pin_fb_obj_dpt()
1239 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);  in intel_pin_fb_obj_dpt()
1265 	vma->display_alignment = max_t(u64, vma->display_alignment, alignment);  in intel_pin_fb_obj_dpt()
1271 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);  in intel_pin_fb_obj_dpt()
1283 	struct drm_device *dev = fb->dev;  in intel_pin_and_fence_fb_obj()
1294 		return ERR_PTR(-EINVAL);  in intel_pin_and_fence_fb_obj()
1301 		return ERR_PTR(-EINVAL);  in intel_pin_and_fence_fb_obj()
1306 	 * the VT-d warning.  in intel_pin_and_fence_fb_obj()
1318 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_pin_and_fence_fb_obj()
1320 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);  in intel_pin_and_fence_fb_obj()
1358 		 * Install a fence for tiled scan-out. Pre-i965 always needs a  in intel_pin_and_fence_fb_obj()
1381 		if (vma->fence)  in intel_pin_and_fence_fb_obj()
1390 	if (ret == -EDEADLK) {  in intel_pin_and_fence_fb_obj()
1399 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);  in intel_pin_and_fence_fb_obj()
1400 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);  in intel_pin_and_fence_fb_obj()
1415  * offset is only used with linear buffers on pre-hsw and tiled buffers
1422 	const struct drm_framebuffer *fb = state->hw.fb;  in intel_fb_xy_to_linear()
1423 	unsigned int cpp = fb->format->cpp[color_plane];  in intel_fb_xy_to_linear()
1424 	unsigned int pitch = state->view.color_plane[color_plane].stride;  in intel_fb_xy_to_linear()
1430  * Add the x/y offsets derived from fb->offsets[] to the user
1439 	*x += state->view.color_plane[color_plane].x;  in intel_add_fb_offsets()
1440 	*y += state->view.color_plane[color_plane].y;  in intel_add_fb_offsets()
1461  * "The Color Control Surface (CCS) contains the compression status of
1462  *  the cache-line pairs. The compression state of the cache-line pair
1463  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
1464  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1465  *  cache-line-pairs. CCS is always Y tiled."
1468  * each cache line in the CCS corresponds to an area of 32x16 cache
1470  * us a ratio of one byte in the CCS for each 8x16 pixels in the
1485  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1486  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1487  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1488  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1569 	switch (cmd->modifier[0]) {  in intel_get_format_info()
1574 					  cmd->pixel_format);  in intel_get_format_info()
1579 					  cmd->pixel_format);  in intel_get_format_info()
1583 					  cmd->pixel_format);  in intel_get_format_info()
1591 	return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],  in gen12_ccs_aux_stride()
1613 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
1615 	return plane->max_stride(plane, pixel_format, modifier,  in intel_plane_fb_max_stride()
1627 	 * The new CCS hash mode makes remapping impossible  in intel_fb_max_stride()
1641 	struct drm_i915_private *dev_priv = to_i915(fb->dev);  in intel_fb_stride_alignment()
1646 							   fb->format->format,  in intel_fb_stride_alignment()
1647 							   fb->modifier);  in intel_fb_stride_alignment()
1653 		if (fb->pitches[color_plane] > max_stride &&  in intel_fb_stride_alignment()
1654 		    !is_ccs_modifier(fb->modifier))  in intel_fb_stride_alignment()
1661 	if (is_ccs_modifier(fb->modifier)) {  in intel_fb_stride_alignment()
1672 		    color_plane == 0 && fb->width > 3840)  in intel_fb_stride_alignment()
1692 	if (plane_config->size == 0)  in initial_plane_vma()
1695 	base = round_down(plane_config->base,  in initial_plane_vma()
1697 	size = round_up(plane_config->base + plane_config->size,  in initial_plane_vma()
1699 	size -= base;  in initial_plane_vma()
1707 	    size * 2 > i915->stolen_usable_size)  in initial_plane_vma()
1722 	switch (plane_config->tiling) {  in initial_plane_vma()
1727 		obj->tiling_and_stride =  in initial_plane_vma()
1728 			plane_config->fb->base.pitches[0] |  in initial_plane_vma()
1729 			plane_config->tiling;  in initial_plane_vma()
1732 		MISSING_CASE(plane_config->tiling);  in initial_plane_vma()
1736 	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);  in initial_plane_vma()
1758 	struct drm_device *dev = crtc->base.dev;  in intel_alloc_initial_plane_obj()
1761 	struct drm_framebuffer *fb = &plane_config->fb->base;  in intel_alloc_initial_plane_obj()
1764 	switch (fb->modifier) {  in intel_alloc_initial_plane_obj()
1770 		drm_dbg(&dev_priv->drm,  in intel_alloc_initial_plane_obj()
1772 			fb->modifier);  in intel_alloc_initial_plane_obj()
1780 	mode_cmd.pixel_format = fb->format->format;  in intel_alloc_initial_plane_obj()
1781 	mode_cmd.width = fb->width;  in intel_alloc_initial_plane_obj()
1782 	mode_cmd.height = fb->height;  in intel_alloc_initial_plane_obj()
1783 	mode_cmd.pitches[0] = fb->pitches[0];  in intel_alloc_initial_plane_obj()
1784 	mode_cmd.modifier[0] = fb->modifier;  in intel_alloc_initial_plane_obj()
1788 				   vma->obj, &mode_cmd)) {  in intel_alloc_initial_plane_obj()
1789 		drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");  in intel_alloc_initial_plane_obj()
1793 	plane_config->vma = vma;  in intel_alloc_initial_plane_obj()
1806 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
1808 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
1811 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
1813 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
1818 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in fixup_plane_bitmasks()
1826 	crtc_state->enabled_planes = 0;  in fixup_plane_bitmasks()
1827 	crtc_state->active_planes = 0;  in fixup_plane_bitmasks()
1829 	drm_for_each_plane_mask(plane, &dev_priv->drm,  in fixup_plane_bitmasks()
1830 				crtc_state->uapi.plane_mask) {  in fixup_plane_bitmasks()
1831 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in fixup_plane_bitmasks()
1832 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in fixup_plane_bitmasks()
1839 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_disable_noatomic()
1841 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
1843 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
1845 	drm_dbg_kms(&dev_priv->drm,  in intel_plane_disable_noatomic()
1847 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
1848 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
1852 	crtc_state->data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
1853 	crtc_state->min_cdclk[plane->id] = 0;  in intel_plane_disable_noatomic()
1855 	if (plane->id == PLANE_PRIMARY)  in intel_plane_disable_noatomic()
1860 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
1862 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
1865 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
1869 		intel_wait_for_vblank(dev_priv, crtc->pipe);  in intel_plane_disable_noatomic()
1875 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
1876 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);  in intel_plane_disable_noatomic()
1879 	intel_wait_for_vblank(dev_priv, crtc->pipe);  in intel_plane_disable_noatomic()
1884 	struct drm_i915_private *i915 = vm->i915;  in intel_dpt_pin()
1890 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);  in intel_dpt_pin()
1891 	atomic_inc(&i915->gpu_error.pending_fb_pin);  in intel_dpt_pin()
1893 	vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,  in intel_dpt_pin()
1905 	dpt->vma = vma;  in intel_dpt_pin()
1906 	dpt->iomem = iomem;  in intel_dpt_pin()
1911 	atomic_dec(&i915->gpu_error.pending_fb_pin);  in intel_dpt_pin()
1912 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);  in intel_dpt_pin()
1921 	i915_vma_unpin_iomap(dpt->vma);  in intel_dpt_unpin()
1922 	i915_vma_put(dpt->vma);  in intel_dpt_unpin()
1933 	for_each_intel_crtc(&i915->drm, crtc) {  in intel_reuse_initial_plane_obj()
1935 			to_intel_crtc_state(crtc->base.state);  in intel_reuse_initial_plane_obj()
1937 			to_intel_plane(crtc->base.primary);  in intel_reuse_initial_plane_obj()
1939 			to_intel_plane_state(plane->base.state);  in intel_reuse_initial_plane_obj()
1941 		if (!crtc_state->uapi.active)  in intel_reuse_initial_plane_obj()
1944 		if (!plane_state->ggtt_vma)  in intel_reuse_initial_plane_obj()
1947 		if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {  in intel_reuse_initial_plane_obj()
1948 			*fb = plane_state->hw.fb;  in intel_reuse_initial_plane_obj()
1949 			*vma = plane_state->ggtt_vma;  in intel_reuse_initial_plane_obj()
1961 	struct drm_device *dev = crtc->base.dev;  in intel_find_initial_plane_obj()
1964 		to_intel_crtc_state(crtc->base.state);  in intel_find_initial_plane_obj()
1966 		to_intel_plane(crtc->base.primary);  in intel_find_initial_plane_obj()
1968 		to_intel_plane_state(plane->base.state);  in intel_find_initial_plane_obj()
1977 	if (!plane_config->fb)  in intel_find_initial_plane_obj()
1981 		fb = &plane_config->fb->base;  in intel_find_initial_plane_obj()
1982 		vma = plane_config->vma;  in intel_find_initial_plane_obj()
2001 	if (crtc_state->bigjoiner) {  in intel_find_initial_plane_obj()
2003 			crtc_state->bigjoiner_linked_crtc;  in intel_find_initial_plane_obj()
2004 		intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));  in intel_find_initial_plane_obj()
2010 	plane_state->uapi.rotation = plane_config->rotation;  in intel_find_initial_plane_obj()
2012 			   plane_state->uapi.rotation, &plane_state->view);  in intel_find_initial_plane_obj()
2015 	plane_state->ggtt_vma = i915_vma_get(vma);  in intel_find_initial_plane_obj()
2017 	    i915_vma_pin_fence(vma) == 0 && vma->fence)  in intel_find_initial_plane_obj()
2018 		plane_state->flags |= PLANE_HAS_FENCE;  in intel_find_initial_plane_obj()
2020 	plane_state->uapi.src_x = 0;  in intel_find_initial_plane_obj()
2021 	plane_state->uapi.src_y = 0;  in intel_find_initial_plane_obj()
2022 	plane_state->uapi.src_w = fb->width << 16;  in intel_find_initial_plane_obj()
2023 	plane_state->uapi.src_h = fb->height << 16;  in intel_find_initial_plane_obj()
2025 	plane_state->uapi.crtc_x = 0;  in intel_find_initial_plane_obj()
2026 	plane_state->uapi.crtc_y = 0;  in intel_find_initial_plane_obj()
2027 	plane_state->uapi.crtc_w = fb->width;  in intel_find_initial_plane_obj()
2028 	plane_state->uapi.crtc_h = fb->height;  in intel_find_initial_plane_obj()
2030 	if (plane_config->tiling)  in intel_find_initial_plane_obj()
2031 		dev_priv->preserve_bios_swizzle = true;  in intel_find_initial_plane_obj()
2033 	plane_state->uapi.fb = fb;  in intel_find_initial_plane_obj()
2036 	plane_state->uapi.crtc = &crtc->base;  in intel_find_initial_plane_obj()
2041 	atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);  in intel_find_initial_plane_obj()
2050 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
2081 		crtc_state->mode_changed = true;  in __intel_display_resume()
2086 		to_intel_atomic_state(state)->skip_intermediate_wm = true;  in __intel_display_resume()
2090 	drm_WARN_ON(dev, ret == -EDEADLK);  in __intel_display_resume()
2096 	return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&  in gpu_reset_clobbers_display()
2097 		intel_has_gpu_reset(&dev_priv->gt));  in gpu_reset_clobbers_display()
2102 	struct drm_device *dev = &dev_priv->drm;  in intel_display_prepare_reset()
2103 	struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;  in intel_display_prepare_reset()
2111 	if (!dev_priv->params.force_reset_modeset_test &&  in intel_display_prepare_reset()
2116 	set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);  in intel_display_prepare_reset()
2118 	wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);  in intel_display_prepare_reset()
2120 	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {  in intel_display_prepare_reset()
2121 		drm_dbg_kms(&dev_priv->drm,  in intel_display_prepare_reset()
2123 		intel_gt_set_wedged(&dev_priv->gt);  in intel_display_prepare_reset()
2128 	 * trample ongoing ->detect() and whatnot.  in intel_display_prepare_reset()
2130 	mutex_lock(&dev->mode_config.mutex);  in intel_display_prepare_reset()
2134 		if (ret != -EDEADLK)  in intel_display_prepare_reset()
2146 		drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",  in intel_display_prepare_reset()
2153 		drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",  in intel_display_prepare_reset()
2159 	dev_priv->modeset_restore_state = state;  in intel_display_prepare_reset()
2160 	state->acquire_ctx = ctx;  in intel_display_prepare_reset()
2165 	struct drm_device *dev = &dev_priv->drm;  in intel_display_finish_reset()
2166 	struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;  in intel_display_finish_reset()
2174 	if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))  in intel_display_finish_reset()
2177 	state = fetch_and_zero(&dev_priv->modeset_restore_state);  in intel_display_finish_reset()
2186 			drm_err(&dev_priv->drm,  in intel_display_finish_reset()
2191 		 * so need a full re-initialization.  in intel_display_finish_reset()
2200 			drm_err(&dev_priv->drm,  in intel_display_finish_reset()
2210 	mutex_unlock(&dev->mode_config.mutex);  in intel_display_finish_reset()
2212 	clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);  in intel_display_finish_reset()
2217 	if (crtc_state->pch_pfit.enabled &&  in underrun_recovery_supported()
2218 	    (crtc_state->pipe_src_w > drm_rect_width(&crtc_state->pch_pfit.dst) ||  in underrun_recovery_supported()
2219 	     crtc_state->pipe_src_h > drm_rect_height(&crtc_state->pch_pfit.dst) ||  in underrun_recovery_supported()
2220 	     crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420))  in underrun_recovery_supported()
2223 	if (crtc_state->dsc.compression_enable)  in underrun_recovery_supported()
2226 	if (crtc_state->has_psr2)  in underrun_recovery_supported()
2229 	if (crtc_state->splitter.enable)  in underrun_recovery_supported()
2237 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
2238 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_set_pipe_chicken()
2239 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
2247 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
2280 	drm_for_each_crtc(crtc, &dev_priv->drm) {  in intel_has_pending_fb_unpin()
2282 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
2283 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
2286 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
2287 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
2306 	mutex_lock(&dev_priv->sb_lock);  in lpt_disable_iclkip()
2312 	mutex_unlock(&dev_priv->sb_lock);  in lpt_disable_iclkip()
2318 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in lpt_program_iclkip()
2319 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in lpt_program_iclkip()
2320 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;  in lpt_program_iclkip()
2327 	 * but the adjusted_mode->crtc_clock in in KHz. To get the  in lpt_program_iclkip()
2339 		divsel = (desired_divisor / iclk_pi_range) - 2;  in lpt_program_iclkip()
2344 		 * out of range for the 7-bit divisor  in lpt_program_iclkip()
2351 	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &  in lpt_program_iclkip()
2353 	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &  in lpt_program_iclkip()
2356 	drm_dbg_kms(&dev_priv->drm,  in lpt_program_iclkip()
2360 	mutex_lock(&dev_priv->sb_lock);  in lpt_program_iclkip()
2383 	mutex_unlock(&dev_priv->sb_lock);  in lpt_program_iclkip()
2402 	mutex_lock(&dev_priv->sb_lock);  in lpt_get_iclkip()
2406 		mutex_unlock(&dev_priv->sb_lock);  in lpt_get_iclkip()
2420 	mutex_unlock(&dev_priv->sb_lock);  in lpt_get_iclkip()
2431 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pch_transcoder_set_timings()
2432 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pch_transcoder_set_timings()
2433 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_pch_transcoder_set_timings()
2460 	drm_WARN_ON(&dev_priv->drm,  in cpt_set_fdi_bc_bifurcation()
2463 	drm_WARN_ON(&dev_priv->drm,  in cpt_set_fdi_bc_bifurcation()
2471 	drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",  in cpt_set_fdi_bc_bifurcation()
2479 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ivb_update_fdi_bc_bifurcation()
2480 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ivb_update_fdi_bc_bifurcation()
2482 	switch (crtc->pipe) {  in ivb_update_fdi_bc_bifurcation()
2486 		if (crtc_state->fdi_lanes > 2)  in ivb_update_fdi_bc_bifurcation()
2509 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_get_crtc_new_encoder()
2516 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
2517 		if (connector_state->crtc != &crtc->base)  in intel_get_crtc_new_encoder()
2520 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
2524 	drm_WARN(encoder->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
2526 		 num_encoders, pipe_name(crtc->pipe));  in intel_get_crtc_new_encoder()
2533  *   - PCH PLLs
2534  *   - FDI training & RX/TX
2535  *   - update transcoder timings
2536  *   - DP transcoding bits
2537  *   - transcoder
2542 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pch_enable()
2543 	struct drm_device *dev = crtc->base.dev;  in ilk_pch_enable()
2545 	enum pipe pipe = crtc->pipe;  in ilk_pch_enable()
2559 	dev_priv->display.fdi_link_train(crtc, crtc_state);  in ilk_pch_enable()
2569 		if (crtc_state->shared_dpll ==  in ilk_pch_enable()
2582 	 * get_shared_dpll unconditionally resets the pll - we need that to have  in ilk_pch_enable()
2596 			&crtc_state->hw.adjusted_mode;  in ilk_pch_enable()
2608 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)  in ilk_pch_enable()
2610 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)  in ilk_pch_enable()
2613 		port = intel_get_crtc_new_encoder(state, crtc_state)->port;  in ilk_pch_enable()
2625 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in lpt_pch_enable()
2626 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in lpt_pch_enable()
2627 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in lpt_pch_enable()
2649 			drm_err(&dev_priv->drm,  in cpt_verify_modeset()
2657 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pfit_enable()
2658 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_enable()
2659 	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;  in ilk_pfit_enable()
2660 	enum pipe pipe = crtc->pipe;  in ilk_pfit_enable()
2663 	int x = dst->x1;  in ilk_pfit_enable()
2664 	int y = dst->y1;  in ilk_pfit_enable()
2666 	if (!crtc_state->pch_pfit.enabled)  in ilk_pfit_enable()
2669 	/* Force use of hard-coded filter coefficients  in ilk_pfit_enable()
2670 	 * as some pre-programmed values are broken,  in ilk_pfit_enable()
2685 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_enable_ips()
2686 	struct drm_device *dev = crtc->base.dev;  in hsw_enable_ips()
2689 	if (!crtc_state->ips_enabled)  in hsw_enable_ips()
2697 	drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));  in hsw_enable_ips()
2715 			drm_err(&dev_priv->drm,  in hsw_enable_ips()
2722 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_disable_ips()
2723 	struct drm_device *dev = crtc->base.dev;  in hsw_disable_ips()
2726 	if (!crtc_state->ips_enabled)  in hsw_disable_ips()
2738 			drm_err(&dev_priv->drm,  in hsw_disable_ips()
2746 	intel_wait_for_vblank(dev_priv, crtc->pipe);  in hsw_disable_ips()
2751 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
2752 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
2762 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in hsw_pre_update_disable_ips()
2763 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_pre_update_disable_ips()
2765 	if (!old_crtc_state->ips_enabled)  in hsw_pre_update_disable_ips()
2778 	    (new_crtc_state->uapi.color_mgmt_changed ||  in hsw_pre_update_disable_ips()
2779 	     new_crtc_state->update_pipe) &&  in hsw_pre_update_disable_ips()
2780 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_pre_update_disable_ips()
2783 	return !new_crtc_state->ips_enabled;  in hsw_pre_update_disable_ips()
2789 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in hsw_post_update_enable_ips()
2790 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_post_update_enable_ips()
2792 	if (!new_crtc_state->ips_enabled)  in hsw_post_update_enable_ips()
2802 	 * Re-enable IPS after the LUT has been programmed.  in hsw_post_update_enable_ips()
2805 	    (new_crtc_state->uapi.color_mgmt_changed ||  in hsw_post_update_enable_ips()
2806 	     new_crtc_state->update_pipe) &&  in hsw_post_update_enable_ips()
2807 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_post_update_enable_ips()
2814 	if (new_crtc_state->update_pipe && old_crtc_state->inherited)  in hsw_post_update_enable_ips()
2817 	return !old_crtc_state->ips_enabled;  in hsw_post_update_enable_ips()
2822 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_nv12_wa()
2824 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
2836 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_scalerclk_wa()
2839 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)  in needs_scalerclk_wa()
2848 	return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&  in planes_enabling()
2849 		new_crtc_state->active_planes;  in planes_enabling()
2855 	return old_crtc_state->active_planes &&  in planes_disabling()
2856 		(!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));  in planes_disabling()
2862 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_post_plane_update()
2867 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
2869 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);  in intel_post_plane_update()
2871 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
2893 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
2899 		if (plane->enable_flip_done &&  in intel_crtc_enable_flip_done()
2900 		    plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
2901 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
2902 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
2911 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
2917 		if (plane->disable_flip_done &&  in intel_crtc_disable_flip_done()
2918 		    plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
2919 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
2920 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
2927 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_crtc_async_flip_disable_wa()
2932 	u8 update_planes = new_crtc_state->update_planes;  in intel_crtc_async_flip_disable_wa()
2939 		if (plane->need_async_flip_disable_wa &&  in intel_crtc_async_flip_disable_wa()
2940 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
2941 		    update_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
2946 			plane->async_flip(plane, old_crtc_state,  in intel_crtc_async_flip_disable_wa()
2953 		intel_wait_for_vblank(i915, crtc->pipe);  in intel_crtc_async_flip_disable_wa()
2959 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_pre_plane_update()
2964 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
2984 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
2986 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
2989 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
2991 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
2992 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))  in intel_pre_plane_update()
2997 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
3002 	if (old_crtc_state->hw.active &&  in intel_pre_plane_update()
3003 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))  in intel_pre_plane_update()
3008 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
3013 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
3014 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
3015 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
3025 		if (dev_priv->display.initial_watermarks)  in intel_pre_plane_update()
3026 			dev_priv->display.initial_watermarks(state, crtc);  in intel_pre_plane_update()
3027 		else if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
3046 	if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)  in intel_pre_plane_update()
3053 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_planes()
3056 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
3065 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
3066 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
3071 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
3072 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
3079  * intel_connector_primary_encoder - get the primary encoder for a connector
3083  * all connectors to their encoder, except for DP-MST connectors which have
3084  * both a virtual and a primary encoder. These DP-MST primary encoders can be
3085  * pointed to by as many DP-MST connectors as there are pipes.
3092 	if (connector->mst_port)  in intel_connector_primary_encoder()
3093 		return &dp_to_dig_port(connector->mst_port)->base;  in intel_connector_primary_encoder()
3096 	drm_WARN_ON(connector->base.dev, !encoder);  in intel_connector_primary_encoder()
3107 	for_each_new_connector_in_state(&state->base, connector, new_conn_state,  in intel_encoders_update_prepare()
3118 		if (!encoder->update_prepare)  in intel_encoders_update_prepare()
3121 		crtc = new_conn_state->crtc ?  in intel_encoders_update_prepare()
3122 			to_intel_crtc(new_conn_state->crtc) : NULL;  in intel_encoders_update_prepare()
3123 		encoder->update_prepare(state, encoder, crtc);  in intel_encoders_update_prepare()
3133 	for_each_new_connector_in_state(&state->base, connector, new_conn_state,  in intel_encoders_update_complete()
3144 		if (!encoder->update_complete)  in intel_encoders_update_complete()
3147 		crtc = new_conn_state->crtc ?  in intel_encoders_update_complete()
3148 			to_intel_crtc(new_conn_state->crtc) : NULL;  in intel_encoders_update_complete()
3149 		encoder->update_complete(state, encoder, crtc);  in intel_encoders_update_complete()
3162 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
3164 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
3166 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
3169 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
3170 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
3184 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
3186 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
3188 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
3191 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
3192 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
3206 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
3208 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
3210 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
3213 		if (encoder->enable)  in intel_encoders_enable()
3214 			encoder->enable(state, encoder,  in intel_encoders_enable()
3229 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_pre_disable()
3231 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_pre_disable()
3233 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_pre_disable()
3236 		if (encoder->pre_disable)  in intel_encoders_pre_disable()
3237 			encoder->pre_disable(state, encoder, old_crtc_state,  in intel_encoders_pre_disable()
3251 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
3253 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
3255 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
3259 		if (encoder->disable)  in intel_encoders_disable()
3260 			encoder->disable(state, encoder,  in intel_encoders_disable()
3274 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
3276 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
3278 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
3281 		if (encoder->post_disable)  in intel_encoders_post_disable()
3282 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
3296 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
3298 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
3300 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
3303 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
3304 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
3318 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
3320 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
3322 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
3325 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
3326 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
3333 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_disable_primary_plane()
3334 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);  in intel_disable_primary_plane()
3336 	plane->disable_plane(plane, crtc_state);  in intel_disable_primary_plane()
3344 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_enable()
3345 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
3347 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in ilk_crtc_enable()
3363 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
3372 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
3374 					     &new_crtc_state->fdi_m_n, NULL);  in ilk_crtc_enable()
3378 	crtc->active = true;  in ilk_crtc_enable()
3382 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
3403 	if (dev_priv->display.initial_watermarks)  in ilk_crtc_enable()
3404 		dev_priv->display.initial_watermarks(state, crtc);  in ilk_crtc_enable()
3407 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
3423 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
3434 	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
3453 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_pipe_mbus_enable()
3454 	enum pipe pipe = crtc->pipe;  in icl_pipe_mbus_enable()
3457 	/* Wa_22010947358:adl-p */  in icl_pipe_mbus_enable()
3476 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
3477 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_linetime_wm()
3479 	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
3480 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
3481 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
3486 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_frame_start_delay()
3487 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_frame_start_delay()
3488 	i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);  in hsw_set_frame_start_delay()
3493 	val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in hsw_set_frame_start_delay()
3500 	struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);  in icl_ddi_bigjoiner_pre_enable()
3501 	struct drm_i915_private *dev_priv = to_i915(master->base.dev);  in icl_ddi_bigjoiner_pre_enable()
3508 	if (crtc_state->bigjoiner_slave)  in icl_ddi_bigjoiner_pre_enable()
3509 		master = crtc_state->bigjoiner_linked_crtc;  in icl_ddi_bigjoiner_pre_enable()
3513 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in icl_ddi_bigjoiner_pre_enable()
3514 		if (conn_state->crtc != &master->base)  in icl_ddi_bigjoiner_pre_enable()
3517 		encoder = to_intel_encoder(conn_state->best_encoder);  in icl_ddi_bigjoiner_pre_enable()
3521 	if (!crtc_state->bigjoiner_slave) {  in icl_ddi_bigjoiner_pre_enable()
3522 		/* need to enable VDSC, which we skipped in pre-enable */  in icl_ddi_bigjoiner_pre_enable()
3526 		 * Enable sequence steps 1-7 on bigjoiner master  in icl_ddi_bigjoiner_pre_enable()
3529 		if (master_crtc_state->shared_dpll)  in icl_ddi_bigjoiner_pre_enable()
3546 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_crtc_enable()
3547 	enum pipe pipe = crtc->pipe, hsw_workaround_pipe;  in hsw_crtc_enable()
3548 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
3551 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in hsw_crtc_enable()
3554 	if (!new_crtc_state->bigjoiner) {  in hsw_crtc_enable()
3557 		if (new_crtc_state->shared_dpll)  in hsw_crtc_enable()
3569 	if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {  in hsw_crtc_enable()
3574 				       new_crtc_state->pixel_multiplier - 1);  in hsw_crtc_enable()
3576 		if (new_crtc_state->has_pch_encoder)  in hsw_crtc_enable()
3578 						     &new_crtc_state->fdi_m_n, NULL);  in hsw_crtc_enable()
3586 	crtc->active = true;  in hsw_crtc_enable()
3590 		new_crtc_state->pch_pfit.enabled;  in hsw_crtc_enable()
3614 	if (dev_priv->display.initial_watermarks)  in hsw_crtc_enable()
3615 		dev_priv->display.initial_watermarks(state, crtc);  in hsw_crtc_enable()
3621 		icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);  in hsw_crtc_enable()
3624 	if (new_crtc_state->bigjoiner_slave)  in hsw_crtc_enable()
3636 	hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
3645 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in ilk_pfit_disable()
3646 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_disable()
3647 	enum pipe pipe = crtc->pipe;  in ilk_pfit_disable()
3651 	if (!old_crtc_state->pch_pfit.enabled)  in ilk_pfit_disable()
3664 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_disable()
3665 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
3683 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
3688 	if (old_crtc_state->has_pch_encoder) {  in ilk_crtc_disable()
3721 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
3729 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_pfit_enable()
3730 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_enable()
3732 	if (!crtc_state->gmch_pfit.control)  in i9xx_pfit_enable()
3739 	drm_WARN_ON(&dev_priv->drm,  in i9xx_pfit_enable()
3741 	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_pfit_enable()
3744 		       crtc_state->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
3745 	intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);  in i9xx_pfit_enable()
3749 	intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);  in i9xx_pfit_enable()
3807 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
3809 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
3811 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
3813 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
3817 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
3826 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
3828 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
3861 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_aux_power_domain()
3862 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);  in intel_aux_power_domain()
3865 	    dig_port->tc_mode == TC_PORT_TBT_ALT) {  in intel_aux_power_domain()
3866 		switch (dig_port->aux_ch) {  in intel_aux_power_domain()
3882 			MISSING_CASE(dig_port->aux_ch);  in intel_aux_power_domain()
3887 	return intel_legacy_aux_to_power_domain(dig_port->aux_ch);  in intel_aux_power_domain()
3924 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
3925 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in get_crtc_power_domains()
3927 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
3929 	enum transcoder transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
3931 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
3936 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
3937 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
3940 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,  in get_crtc_power_domains()
3941 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
3944 		mask |= BIT_ULL(intel_encoder->power_domain);  in get_crtc_power_domains()
3947 	if (HAS_DDI(dev_priv) && crtc_state->has_audio)  in get_crtc_power_domains()
3950 	if (crtc_state->shared_dpll)  in get_crtc_power_domains()
3953 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
3962 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in modeset_get_crtc_power_domains()
3963 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in modeset_get_crtc_power_domains()
3969 	new_domains = domains & ~crtc->enabled_power_domains.mask;  in modeset_get_crtc_power_domains()
3970 	old_domains = crtc->enabled_power_domains.mask & ~domains;  in modeset_get_crtc_power_domains()
3974 					       &crtc->enabled_power_domains,  in modeset_get_crtc_power_domains()
3983 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),  in modeset_put_crtc_power_domains()
3984 					    &crtc->enabled_power_domains,  in modeset_put_crtc_power_domains()
3993 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in valleyview_crtc_enable()
3994 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
3996 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in valleyview_crtc_enable()
4012 	crtc->active = true;  in valleyview_crtc_enable()
4035 	dev_priv->display.initial_watermarks(state, crtc);  in valleyview_crtc_enable()
4045 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_set_pll_dividers()
4046 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_set_pll_dividers()
4048 	intel_de_write(dev_priv, FP0(crtc->pipe),  in i9xx_set_pll_dividers()
4049 		       crtc_state->dpll_hw_state.fp0);  in i9xx_set_pll_dividers()
4050 	intel_de_write(dev_priv, FP1(crtc->pipe),  in i9xx_set_pll_dividers()
4051 		       crtc_state->dpll_hw_state.fp1);  in i9xx_set_pll_dividers()
4059 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_enable()
4060 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
4062 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in i9xx_crtc_enable()
4075 	crtc->active = true;  in i9xx_crtc_enable()
4091 	if (dev_priv->display.initial_watermarks)  in i9xx_crtc_enable()
4092 		dev_priv->display.initial_watermarks(state, crtc);  in i9xx_crtc_enable()
4108 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in i9xx_pfit_disable()
4109 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_disable()
4111 	if (!old_crtc_state->gmch_pfit.control)  in i9xx_pfit_disable()
4114 	assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);  in i9xx_pfit_disable()
4116 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",  in i9xx_pfit_disable()
4126 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_disable()
4127 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
4160 	if (!dev_priv->display.initial_watermarks)  in i9xx_crtc_disable()
4172 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_noatomic()
4174 		to_intel_bw_state(dev_priv->bw_obj.state);  in intel_crtc_disable_noatomic()
4176 		to_intel_cdclk_state(dev_priv->cdclk.obj.state);  in intel_crtc_disable_noatomic()
4178 		to_intel_dbuf_state(dev_priv->dbuf.obj.state);  in intel_crtc_disable_noatomic()
4180 		to_intel_crtc_state(crtc->base.state);  in intel_crtc_disable_noatomic()
4184 	enum pipe pipe = crtc->pipe;  in intel_crtc_disable_noatomic()
4187 	if (!crtc_state->hw.active)  in intel_crtc_disable_noatomic()
4190 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_crtc_disable_noatomic()
4192 			to_intel_plane_state(plane->base.state);  in intel_crtc_disable_noatomic()
4194 		if (plane_state->uapi.visible)  in intel_crtc_disable_noatomic()
4198 	state = drm_atomic_state_alloc(&dev_priv->drm);  in intel_crtc_disable_noatomic()
4200 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_disable_noatomic()
4202 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_disable_noatomic()
4206 	state->acquire_ctx = ctx;  in intel_crtc_disable_noatomic()
4208 	/* Everything's already locked, -EDEADLK can't happen. */  in intel_crtc_disable_noatomic()
4210 	ret = drm_atomic_add_affected_connectors(state, &crtc->base);  in intel_crtc_disable_noatomic()
4212 	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);  in intel_crtc_disable_noatomic()
4214 	dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);  in intel_crtc_disable_noatomic()
4218 	drm_dbg_kms(&dev_priv->drm,  in intel_crtc_disable_noatomic()
4220 		    crtc->base.base.id, crtc->base.name);  in intel_crtc_disable_noatomic()
4222 	crtc->active = false;  in intel_crtc_disable_noatomic()
4223 	crtc->base.enabled = false;  in intel_crtc_disable_noatomic()
4225 	drm_WARN_ON(&dev_priv->drm,  in intel_crtc_disable_noatomic()
4226 		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);  in intel_crtc_disable_noatomic()
4227 	crtc_state->uapi.active = false;  in intel_crtc_disable_noatomic()
4228 	crtc_state->uapi.connector_mask = 0;  in intel_crtc_disable_noatomic()
4229 	crtc_state->uapi.encoder_mask = 0;  in intel_crtc_disable_noatomic()
4231 	memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));  in intel_crtc_disable_noatomic()
4233 	for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)  in intel_crtc_disable_noatomic()
4234 		encoder->base.crtc = NULL;  in intel_crtc_disable_noatomic()
4240 	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);  in intel_crtc_disable_noatomic()
4242 	dev_priv->active_pipes &= ~BIT(pipe);  in intel_crtc_disable_noatomic()
4243 	cdclk_state->min_cdclk[pipe] = 0;  in intel_crtc_disable_noatomic()
4244 	cdclk_state->min_voltage_level[pipe] = 0;  in intel_crtc_disable_noatomic()
4245 	cdclk_state->active_pipes &= ~BIT(pipe);  in intel_crtc_disable_noatomic()
4247 	dbuf_state->active_pipes &= ~BIT(pipe);  in intel_crtc_disable_noatomic()
4249 	bw_state->data_rate[pipe] = 0;  in intel_crtc_disable_noatomic()
4250 	bw_state->num_active_planes[pipe] = 0;  in intel_crtc_disable_noatomic()
4269 		drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",  in intel_display_suspend()
4272 		dev_priv->modeset_restore_state = state;  in intel_display_suspend()
4289 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in intel_connector_verify_state()
4290 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_connector_verify_state()
4292 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",  in intel_connector_verify_state()
4293 		    connector->base.base.id, connector->base.name);  in intel_connector_verify_state()
4295 	if (connector->get_hw_state(connector)) {  in intel_connector_verify_state()
4304 		I915_STATE_WARN(!crtc_state->hw.active,  in intel_connector_verify_state()
4307 		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)  in intel_connector_verify_state()
4310 		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,  in intel_connector_verify_state()
4313 		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,  in intel_connector_verify_state()
4316 		I915_STATE_WARN(crtc_state && crtc_state->hw.active,  in intel_connector_verify_state()
4318 		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,  in intel_connector_verify_state()
4325 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_crtc_state_ips_capable()
4326 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_crtc_state_ips_capable()
4332 	if (!dev_priv->params.enable_ips)  in hsw_crtc_state_ips_capable()
4335 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
4346 	    crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)  in hsw_crtc_state_ips_capable()
4355 		to_i915(crtc_state->uapi.crtc->dev);  in hsw_compute_ips_config()
4357 		to_intel_atomic_state(crtc_state->uapi.state);  in hsw_compute_ips_config()
4359 	crtc_state->ips_enabled = false;  in hsw_compute_ips_config()
4370 	if (crtc_state->crc_enabled)  in hsw_compute_ips_config()
4374 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))  in hsw_compute_ips_config()
4385 		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)  in hsw_compute_ips_config()
4389 	crtc_state->ips_enabled = true;  in hsw_compute_ips_config()
4396 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_supports_double_wide()
4400 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));  in intel_crtc_supports_double_wide()
4405 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
4409 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
4410 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
4413 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
4417 		      crtc_state->pipe_src_w << 16,  in ilk_pipe_pixel_rate()
4418 		      crtc_state->pipe_src_h << 16);  in ilk_pipe_pixel_rate()
4420 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
4427 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
4428 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
4429 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
4430 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
4432 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
4433 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
4434 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
4435 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
4437 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
4438 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
4440 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
4447 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_crtc_compute_pixel_rate()
4451 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
4452 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
4454 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
4460 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()
4461 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
4462 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
4466 	if (crtc_state->bigjoiner) {  in intel_crtc_readout_derived_state()
4471 		pipe_mode->crtc_hdisplay /= 2;  in intel_crtc_readout_derived_state()
4472 		pipe_mode->crtc_hblank_start /= 2;  in intel_crtc_readout_derived_state()
4473 		pipe_mode->crtc_hblank_end /= 2;  in intel_crtc_readout_derived_state()
4474 		pipe_mode->crtc_hsync_start /= 2;  in intel_crtc_readout_derived_state()
4475 		pipe_mode->crtc_hsync_end /= 2;  in intel_crtc_readout_derived_state()
4476 		pipe_mode->crtc_htotal /= 2;  in intel_crtc_readout_derived_state()
4477 		pipe_mode->crtc_clock /= 2;  in intel_crtc_readout_derived_state()
4480 	if (crtc_state->splitter.enable) {  in intel_crtc_readout_derived_state()
4481 		int n = crtc_state->splitter.link_count;  in intel_crtc_readout_derived_state()
4482 		int overlap = crtc_state->splitter.pixel_overlap;  in intel_crtc_readout_derived_state()
4488 		 * h_full = (h_segment - pixel_overlap) * link_count  in intel_crtc_readout_derived_state()
4490 		pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;  in intel_crtc_readout_derived_state()
4491 		pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;  in intel_crtc_readout_derived_state()
4492 		pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;  in intel_crtc_readout_derived_state()
4493 		pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;  in intel_crtc_readout_derived_state()
4494 		pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;  in intel_crtc_readout_derived_state()
4495 		pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;  in intel_crtc_readout_derived_state()
4496 		pipe_mode->crtc_clock *= n;  in intel_crtc_readout_derived_state()
4508 	mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;  in intel_crtc_readout_derived_state()
4509 	mode->vdisplay = crtc_state->pipe_src_h;  in intel_crtc_readout_derived_state()
4515 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
4523 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_compute_config()
4524 	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;  in intel_crtc_compute_config()
4525 	int clock_limit = dev_priv->max_dotclk_freq;  in intel_crtc_compute_config()
4527 	drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);  in intel_crtc_compute_config()
4530 	if (pipe_config->bigjoiner) {  in intel_crtc_compute_config()
4531 		pipe_mode->crtc_clock /= 2;  in intel_crtc_compute_config()
4532 		pipe_mode->crtc_hdisplay /= 2;  in intel_crtc_compute_config()
4533 		pipe_mode->crtc_hblank_start /= 2;  in intel_crtc_compute_config()
4534 		pipe_mode->crtc_hblank_end /= 2;  in intel_crtc_compute_config()
4535 		pipe_mode->crtc_hsync_start /= 2;  in intel_crtc_compute_config()
4536 		pipe_mode->crtc_hsync_end /= 2;  in intel_crtc_compute_config()
4537 		pipe_mode->crtc_htotal /= 2;  in intel_crtc_compute_config()
4538 		pipe_config->pipe_src_w /= 2;  in intel_crtc_compute_config()
4541 	if (pipe_config->splitter.enable) {  in intel_crtc_compute_config()
4542 		int n = pipe_config->splitter.link_count;  in intel_crtc_compute_config()
4543 		int overlap = pipe_config->splitter.pixel_overlap;  in intel_crtc_compute_config()
4545 		pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;  in intel_crtc_compute_config()
4546 		pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;  in intel_crtc_compute_config()
4547 		pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;  in intel_crtc_compute_config()
4548 		pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;  in intel_crtc_compute_config()
4549 		pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;  in intel_crtc_compute_config()
4550 		pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;  in intel_crtc_compute_config()
4551 		pipe_mode->crtc_clock *= n;  in intel_crtc_compute_config()
4557 		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;  in intel_crtc_compute_config()
4564 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_config()
4565 			clock_limit = dev_priv->max_dotclk_freq;  in intel_crtc_compute_config()
4566 			pipe_config->double_wide = true;  in intel_crtc_compute_config()
4570 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_config()
4571 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_compute_config()
4573 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_config()
4574 			    yesno(pipe_config->double_wide));  in intel_crtc_compute_config()
4575 		return -EINVAL;  in intel_crtc_compute_config()
4580 	 * - DVO ganged mode  in intel_crtc_compute_config()
4581 	 * - LVDS dual channel mode  in intel_crtc_compute_config()
4582 	 * - Double wide pipe  in intel_crtc_compute_config()
4584 	if (pipe_config->pipe_src_w & 1) {  in intel_crtc_compute_config()
4585 		if (pipe_config->double_wide) {  in intel_crtc_compute_config()
4586 			drm_dbg_kms(&dev_priv->drm,  in intel_crtc_compute_config()
4588 			return -EINVAL;  in intel_crtc_compute_config()
4593 			drm_dbg_kms(&dev_priv->drm,  in intel_crtc_compute_config()
4595 			return -EINVAL;  in intel_crtc_compute_config()
4603 	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)  in intel_crtc_compute_config()
4604 		return -EINVAL;  in intel_crtc_compute_config()
4608 	if (pipe_config->has_pch_encoder)  in intel_crtc_compute_config()
4655 	m_n->tu = 64;  in intel_link_compute_m_n()
4658 		    &m_n->gmch_m, &m_n->gmch_n,  in intel_link_compute_m_n()
4662 		    &m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
4679 		if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
4680 			drm_dbg_kms(&dev_priv->drm,  in intel_panel_sanitize_ssc()
4683 				    enableddisabled(dev_priv->vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
4684 			dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
4692 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_pch_transcoder_set_m_n()
4693 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pch_transcoder_set_m_n()
4694 	enum pipe pipe = crtc->pipe;  in intel_pch_transcoder_set_m_n()
4697 		       TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_pch_transcoder_set_m_n()
4698 	intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);  in intel_pch_transcoder_set_m_n()
4699 	intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);  in intel_pch_transcoder_set_m_n()
4700 	intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);  in intel_pch_transcoder_set_m_n()
4720 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_cpu_transcoder_set_m_n()
4721 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m_n()
4722 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m_n()
4723 	enum transcoder transcoder = crtc_state->cpu_transcoder;  in intel_cpu_transcoder_set_m_n()
4727 			       TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
4729 			       m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
4731 			       m_n->link_m);  in intel_cpu_transcoder_set_m_n()
4733 			       m_n->link_n);  in intel_cpu_transcoder_set_m_n()
4738 		if (m2_n2 && crtc_state->has_drrs &&  in intel_cpu_transcoder_set_m_n()
4741 				       TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);  in intel_cpu_transcoder_set_m_n()
4743 				       m2_n2->gmch_n);  in intel_cpu_transcoder_set_m_n()
4745 				       m2_n2->link_m);  in intel_cpu_transcoder_set_m_n()
4747 				       m2_n2->link_n);  in intel_cpu_transcoder_set_m_n()
4751 			       TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
4752 		intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
4753 		intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
4754 		intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
4761 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in intel_dp_set_m_n()
4764 		dp_m_n = &crtc_state->dp_m_n;  in intel_dp_set_m_n()
4765 		dp_m2_n2 = &crtc_state->dp_m2_n2;  in intel_dp_set_m_n()
4772 		dp_m_n = &crtc_state->dp_m2_n2;  in intel_dp_set_m_n()
4774 		drm_err(&i915->drm, "Unsupported divider value\n");  in intel_dp_set_m_n()
4778 	if (crtc_state->has_pch_encoder)  in intel_dp_set_m_n()
4779 		intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);  in intel_dp_set_m_n()
4786 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
4787 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings()
4788 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
4789 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
4790 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
4796 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
4797 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
4799 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
4801 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
4802 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
4805 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
4807 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
4808 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
4810 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
4818 		       (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));  in intel_set_transcoder_timings()
4820 		       (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));  in intel_set_transcoder_timings()
4822 		       (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));  in intel_set_transcoder_timings()
4825 		       (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));  in intel_set_transcoder_timings()
4827 		       (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));  in intel_set_transcoder_timings()
4829 		       (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));  in intel_set_transcoder_timings()
4844 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
4845 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_pipe_src_size()
4846 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
4852 		       ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));  in intel_set_pipe_src_size()
4857 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_pipe_is_interlaced()
4858 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
4873 	struct drm_device *dev = crtc->base.dev;  in intel_get_transcoder_timings()
4875 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
4879 	pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;  in intel_get_transcoder_timings()
4880 	pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;  in intel_get_transcoder_timings()
4884 		pipe_config->hw.adjusted_mode.crtc_hblank_start =  in intel_get_transcoder_timings()
4886 		pipe_config->hw.adjusted_mode.crtc_hblank_end =  in intel_get_transcoder_timings()
4890 	pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;  in intel_get_transcoder_timings()
4891 	pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;  in intel_get_transcoder_timings()
4894 	pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;  in intel_get_transcoder_timings()
4895 	pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;  in intel_get_transcoder_timings()
4899 		pipe_config->hw.adjusted_mode.crtc_vblank_start =  in intel_get_transcoder_timings()
4901 		pipe_config->hw.adjusted_mode.crtc_vblank_end =  in intel_get_transcoder_timings()
4905 	pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;  in intel_get_transcoder_timings()
4906 	pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;  in intel_get_transcoder_timings()
4909 		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
4910 		pipe_config->hw.adjusted_mode.crtc_vtotal += 1;  in intel_get_transcoder_timings()
4911 		pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;  in intel_get_transcoder_timings()
4918 	struct drm_device *dev = crtc->base.dev;  in intel_get_pipe_src_size()
4922 	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));  in intel_get_pipe_src_size()
4923 	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;  in intel_get_pipe_src_size()
4924 	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;  in intel_get_pipe_src_size()
4929 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_set_pipeconf()
4930 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_set_pipeconf()
4937 		pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;  in i9xx_set_pipeconf()
4939 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
4946 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
4950 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
4966 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
4977 	     crtc_state->limited_color_range)  in i9xx_set_pipeconf()
4980 	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
4982 	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in i9xx_set_pipeconf()
4984 	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
4985 	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));  in i9xx_set_pipeconf()
4999 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_get_pfit_config()
5000 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pfit_config()
5012 		if (crtc->pipe != PIPE_B)  in i9xx_get_pfit_config()
5015 		if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))  in i9xx_get_pfit_config()
5019 	crtc_state->gmch_pfit.control = tmp;  in i9xx_get_pfit_config()
5020 	crtc_state->gmch_pfit.pgm_ratios =  in i9xx_get_pfit_config()
5027 	struct drm_device *dev = crtc->base.dev;  in vlv_crtc_clock_get()
5029 	enum pipe pipe = crtc->pipe;  in vlv_crtc_clock_get()
5035 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in vlv_crtc_clock_get()
5048 	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);  in vlv_crtc_clock_get()
5054 	struct drm_device *dev = crtc->base.dev;  in chv_crtc_clock_get()
5056 	enum pipe pipe = crtc->pipe;  in chv_crtc_clock_get()
5063 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in chv_crtc_clock_get()
5082 	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);  in chv_crtc_clock_get()
5088 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipemisc_output_format()
5091 	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));  in bdw_get_pipemisc_output_format()
5095 		drm_WARN_ON(&dev_priv->drm,  in bdw_get_pipemisc_output_format()
5108 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_get_pipe_color_config()
5109 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);  in i9xx_get_pipe_color_config()
5110 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pipe_color_config()
5111 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_get_pipe_color_config()
5117 		crtc_state->gamma_enable = true;  in i9xx_get_pipe_color_config()
5121 		crtc_state->csc_enable = true;  in i9xx_get_pipe_color_config()
5127 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pipe_config()
5133 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
5138 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
5139 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in i9xx_get_pipe_config()
5140 	pipe_config->shared_dpll = NULL;  in i9xx_get_pipe_config()
5144 	tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));  in i9xx_get_pipe_config()
5152 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
5155 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
5158 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
5167 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
5169 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>  in i9xx_get_pipe_config()
5173 		pipe_config->cgm_mode = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
5174 						      CGM_PIPE_MODE(crtc->pipe));  in i9xx_get_pipe_config()
5180 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
5189 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)  in i9xx_get_pipe_config()
5190 			tmp = dev_priv->chv_dpll_md[crtc->pipe];  in i9xx_get_pipe_config()
5192 			tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));  in i9xx_get_pipe_config()
5193 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
5196 		pipe_config->dpll_hw_state.dpll_md = tmp;  in i9xx_get_pipe_config()
5199 		tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));  in i9xx_get_pipe_config()
5200 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
5205 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
5207 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
5209 	pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
5210 							DPLL(crtc->pipe));  in i9xx_get_pipe_config()
5212 		pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
5213 							       FP0(crtc->pipe));  in i9xx_get_pipe_config()
5214 		pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
5215 							       FP1(crtc->pipe));  in i9xx_get_pipe_config()
5217 		/* Mask out read-only status bits. */  in i9xx_get_pipe_config()
5218 		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |  in i9xx_get_pipe_config()
5235 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
5236 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
5259 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in ilk_init_pch_refclk()
5260 		switch (encoder->type) {  in ilk_init_pch_refclk()
5267 			if (encoder->port == PORT_A)  in ilk_init_pch_refclk()
5276 		has_ck505 = dev_priv->vbt.display_clock_mode;  in ilk_init_pch_refclk()
5284 	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {  in ilk_init_pch_refclk()
5297 	drm_dbg_kms(&dev_priv->drm,  in ilk_init_pch_refclk()
5358 			drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");  in ilk_init_pch_refclk()
5373 				drm_dbg_kms(&dev_priv->drm,  in ilk_init_pch_refclk()
5385 		drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");  in ilk_init_pch_refclk()
5397 			drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");  in ilk_init_pch_refclk()
5425 		drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");  in lpt_reset_fdi_mphy()
5433 		drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");  in lpt_reset_fdi_mphy()
5513  * - Sequence to enable CLKOUT_DP
5514  * - Sequence to enable CLKOUT_DP without spread
5515  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5522 	if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,  in lpt_enable_clkout_dp()
5525 	if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&  in lpt_enable_clkout_dp()
5529 	mutex_lock(&dev_priv->sb_lock);  in lpt_enable_clkout_dp()
5554 	mutex_unlock(&dev_priv->sb_lock);  in lpt_enable_clkout_dp()
5562 	mutex_lock(&dev_priv->sb_lock);  in lpt_disable_clkout_dp()
5580 	mutex_unlock(&dev_priv->sb_lock);  in lpt_disable_clkout_dp()
5597 	[BEND_IDX( -5)] = 0x0025,
5598 	[BEND_IDX(-10)] = 0x0125,
5599 	[BEND_IDX(-15)] = 0x0125,
5600 	[BEND_IDX(-20)] = 0x0225,
5601 	[BEND_IDX(-25)] = 0x0225,
5602 	[BEND_IDX(-30)] = 0x0325,
5603 	[BEND_IDX(-35)] = 0x0325,
5604 	[BEND_IDX(-40)] = 0x0425,
5605 	[BEND_IDX(-45)] = 0x0425,
5606 	[BEND_IDX(-50)] = 0x0525,
5611  * steps -50 to 50 inclusive, in steps of 5
5613  * change in clock period = -(steps / 10) * 5.787 ps
5620 	if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))  in lpt_bend_clkout_dp()
5623 	if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))  in lpt_bend_clkout_dp()
5626 	mutex_lock(&dev_priv->sb_lock);  in lpt_bend_clkout_dp()
5639 	mutex_unlock(&dev_priv->sb_lock);  in lpt_bend_clkout_dp()
5688 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in lpt_init_pch_refclk()
5689 		switch (encoder->type) {  in lpt_init_pch_refclk()
5713 	dev_priv->pch_ssc_use = 0;  in lpt_init_pch_refclk()
5716 		drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");  in lpt_init_pch_refclk()
5717 		dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);  in lpt_init_pch_refclk()
5721 		drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");  in lpt_init_pch_refclk()
5722 		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);  in lpt_init_pch_refclk()
5726 		drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");  in lpt_init_pch_refclk()
5727 		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);  in lpt_init_pch_refclk()
5730 	if (dev_priv->pch_ssc_use)  in lpt_init_pch_refclk()
5754 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_set_pipeconf()
5755 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_set_pipeconf()
5756 	enum pipe pipe = crtc->pipe;  in ilk_set_pipeconf()
5761 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
5779 	if (crtc_state->dither)  in ilk_set_pipeconf()
5782 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
5791 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
5792 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
5794 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
5798 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
5801 	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
5803 	val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in ilk_set_pipeconf()
5811 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_pipeconf()
5812 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_pipeconf()
5813 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_pipeconf()
5816 	if (IS_HASWELL(dev_priv) && crtc_state->dither)  in hsw_set_pipeconf()
5819 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_pipeconf()
5825 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_pipeconf()
5834 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipemisc()
5836 		&crtc_state->scaler_state;  in bdw_set_pipemisc()
5838 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_set_pipemisc()
5842 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipemisc()
5858 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipemisc()
5862 	if (crtc_state->dither)  in bdw_set_pipemisc()
5865 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipemisc()
5866 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipemisc()
5869 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipemisc()
5874 	    (crtc_state->active_planes & ~(icl_hdr_plane_mask() |  in bdw_set_pipemisc()
5884 		for (i = 0; i < crtc->num_scalers; i++) {  in bdw_set_pipemisc()
5885 			if (!scaler_state->scalers[i].in_use)  in bdw_set_pipemisc()
5892 		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),  in bdw_set_pipemisc()
5898 	intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);  in bdw_set_pipemisc()
5903 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipemisc_bpp()
5906 	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));  in bdw_get_pipemisc_bpp()
5923 	 * MIPI DSI HW readout.  in bdw_get_pipemisc_bpp()
5949 	struct drm_device *dev = crtc->base.dev;  in intel_pch_transcoder_get_m_n()
5951 	enum pipe pipe = crtc->pipe;  in intel_pch_transcoder_get_m_n()
5953 	m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));  in intel_pch_transcoder_get_m_n()
5954 	m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));  in intel_pch_transcoder_get_m_n()
5955 	m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))  in intel_pch_transcoder_get_m_n()
5957 	m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));  in intel_pch_transcoder_get_m_n()
5958 	m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))  in intel_pch_transcoder_get_m_n()
5967 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m_n()
5968 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m_n()
5971 		m_n->link_m = intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5973 		m_n->link_n = intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5975 		m_n->gmch_m = intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5978 		m_n->gmch_n = intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5980 		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))  in intel_cpu_transcoder_get_m_n()
5984 			m2_n2->link_m = intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5986 			m2_n2->link_n =	intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5988 			m2_n2->gmch_m =	intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5991 			m2_n2->gmch_n =	intel_de_read(dev_priv,  in intel_cpu_transcoder_get_m_n()
5993 			m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))  in intel_cpu_transcoder_get_m_n()
5997 		m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));  in intel_cpu_transcoder_get_m_n()
5998 		m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));  in intel_cpu_transcoder_get_m_n()
5999 		m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))  in intel_cpu_transcoder_get_m_n()
6001 		m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));  in intel_cpu_transcoder_get_m_n()
6002 		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))  in intel_cpu_transcoder_get_m_n()
6010 	if (pipe_config->has_pch_encoder)  in intel_dp_get_m_n()
6011 		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);  in intel_dp_get_m_n()
6013 		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,  in intel_dp_get_m_n()
6014 					     &pipe_config->dp_m_n,  in intel_dp_get_m_n()
6015 					     &pipe_config->dp_m2_n2);  in intel_dp_get_m_n()
6021 	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,  in ilk_get_fdi_m_n_config()
6022 				     &pipe_config->fdi_m_n, NULL);  in ilk_get_fdi_m_n_config()
6028 	drm_rect_init(&crtc_state->pch_pfit.dst,  in ilk_get_pfit_pos_size()
6035 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_get_pfit_config()
6036 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_get_pfit_config()
6037 	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;  in skl_get_pfit_config()
6038 	int id = -1;  in skl_get_pfit_config()
6042 	for (i = 0; i < crtc->num_scalers; i++) {  in skl_get_pfit_config()
6045 		ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));  in skl_get_pfit_config()
6050 		crtc_state->pch_pfit.enabled = true;  in skl_get_pfit_config()
6052 		pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));  in skl_get_pfit_config()
6053 		size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));  in skl_get_pfit_config()
6057 		scaler_state->scalers[i].in_use = true;  in skl_get_pfit_config()
6061 	scaler_state->scaler_id = id;  in skl_get_pfit_config()
6063 		scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);  in skl_get_pfit_config()
6065 		scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);  in skl_get_pfit_config()
6070 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_get_pfit_config()
6071 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_get_pfit_config()
6074 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));  in ilk_get_pfit_config()
6078 	crtc_state->pch_pfit.enabled = true;  in ilk_get_pfit_config()
6080 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));  in ilk_get_pfit_config()
6081 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));  in ilk_get_pfit_config()
6090 	drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&  in ilk_get_pfit_config()
6091 		    (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));  in ilk_get_pfit_config()
6097 	struct drm_device *dev = crtc->base.dev;  in ilk_get_pipe_config()
6104 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
6109 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in ilk_get_pipe_config()
6110 	pipe_config->shared_dpll = NULL;  in ilk_get_pipe_config()
6113 	tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));  in ilk_get_pipe_config()
6119 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
6122 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
6125 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
6128 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
6135 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
6140 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
6143 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
6147 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>  in ilk_get_pipe_config()
6150 	pipe_config->csc_mode = intel_de_read(dev_priv,  in ilk_get_pipe_config()
6151 					      PIPE_CSC_MODE(crtc->pipe));  in ilk_get_pipe_config()
6156 	if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {  in ilk_get_pipe_config()
6161 		pipe_config->has_pch_encoder = true;  in ilk_get_pipe_config()
6163 		tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));  in ilk_get_pipe_config()
6164 		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>  in ilk_get_pipe_config()
6171 			 * The pipe->pch transcoder and pch transcoder->pll  in ilk_get_pipe_config()
6174 			pll_id = (enum intel_dpll_id) crtc->pipe;  in ilk_get_pipe_config()
6177 			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))  in ilk_get_pipe_config()
6183 		pipe_config->shared_dpll =  in ilk_get_pipe_config()
6185 		pll = pipe_config->shared_dpll;  in ilk_get_pipe_config()
6188 						     &pipe_config->dpll_hw_state);  in ilk_get_pipe_config()
6191 		tmp = pipe_config->dpll_hw_state.dpll;  in ilk_get_pipe_config()
6192 		pipe_config->pixel_multiplier =  in ilk_get_pipe_config()
6198 		pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
6218 	struct drm_device *dev = crtc->base.dev;  in hsw_get_transcoder_state()
6230 	 * The pipe->transcoder mapping is fixed with the exception of the eDP  in hsw_get_transcoder_state()
6233 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_get_transcoder_state()
6281 		if (trans_pipe == crtc->pipe) {  in hsw_get_transcoder_state()
6282 			pipe_config->cpu_transcoder = panel_transcoder;  in hsw_get_transcoder_state()
6283 			pipe_config->pch_pfit.force_thru = force_thru;  in hsw_get_transcoder_state()
6294 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
6297 	tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
6306 	struct drm_device *dev = crtc->base.dev;  in bxt_get_dsi_transcoder_state()
6326 		 * registers/MIPI[BXT]. We can break out here early, since we  in bxt_get_dsi_transcoder_state()
6338 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
6341 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
6345 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
6351 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_get_ddi_port_state()
6352 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in hsw_get_ddi_port_state()
6377 		pipe_config->has_pch_encoder = true;  in hsw_get_ddi_port_state()
6380 		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>  in hsw_get_ddi_port_state()
6390 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_get_pipe_config()
6396 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
6399 	pipe_config->shared_dpll = NULL;  in hsw_get_pipe_config()
6405 		drm_WARN_ON(&dev_priv->drm, active);  in hsw_get_pipe_config()
6410 	if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)  in hsw_get_pipe_config()
6415 		if (!pipe_config->bigjoiner_slave)  in hsw_get_pipe_config()
6419 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
6422 		pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;  in hsw_get_pipe_config()
6423 	} else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
6429 	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))  in hsw_get_pipe_config()
6436 					PIPECONF(pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
6439 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
6441 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
6443 		pipe_config->output_format =  in hsw_get_pipe_config()
6447 	pipe_config->gamma_mode = intel_de_read(dev_priv,  in hsw_get_pipe_config()
6448 						GAMMA_MODE(crtc->pipe));  in hsw_get_pipe_config()
6450 	pipe_config->csc_mode = intel_de_read(dev_priv,  in hsw_get_pipe_config()
6451 					      PIPE_CSC_MODE(crtc->pipe));  in hsw_get_pipe_config()
6454 		tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));  in hsw_get_pipe_config()
6457 			pipe_config->gamma_enable = true;  in hsw_get_pipe_config()
6460 			pipe_config->csc_enable = true;  in hsw_get_pipe_config()
6467 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
6468 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
6470 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
6474 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
6483 			pipe_config->ips_enabled = intel_de_read(dev_priv,  in hsw_get_pipe_config()
6491 			pipe_config->ips_enabled = true;  in hsw_get_pipe_config()
6495 	if (pipe_config->bigjoiner_slave) {  in hsw_get_pipe_config()
6497 		pipe_config->pixel_multiplier = 0;  in hsw_get_pipe_config()
6498 	} else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
6499 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
6500 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
6502 				      PIPE_MULT(pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
6504 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
6515 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
6516 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_get_pipe_config()
6518 	if (!i915->display.get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
6521 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
6543 		return ERR_PTR(-ENOMEM);  in intel_framebuffer_create()
6549 	return &intel_fb->base;  in intel_framebuffer_create()
6568 		if (plane_state->crtc != crtc)  in intel_modeset_disable_planes()
6589 	struct drm_device *dev = encoder->base.dev;  in intel_get_load_detect_pipe()
6591 	struct drm_mode_config *config = &dev->mode_config;  in intel_get_load_detect_pipe()
6597 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",  in intel_get_load_detect_pipe()
6598 		    connector->base.id, connector->name,  in intel_get_load_detect_pipe()
6599 		    encoder->base.base.id, encoder->base.name);  in intel_get_load_detect_pipe()
6601 	old->restore_state = NULL;  in intel_get_load_detect_pipe()
6603 	drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));  in intel_get_load_detect_pipe()
6608 	 *   - if the connector already has an assigned crtc, use it (but make  in intel_get_load_detect_pipe()
6611 	 *   - try to find the first unused crtc that can drive this connector,  in intel_get_load_detect_pipe()
6616 	if (connector->state->crtc) {  in intel_get_load_detect_pipe()
6617 		crtc = to_intel_crtc(connector->state->crtc);  in intel_get_load_detect_pipe()
6619 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_get_load_detect_pipe()
6629 		if (!(encoder->base.possible_crtcs &  in intel_get_load_detect_pipe()
6630 		      drm_crtc_mask(&possible_crtc->base)))  in intel_get_load_detect_pipe()
6633 		ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);  in intel_get_load_detect_pipe()
6637 		if (possible_crtc->base.state->enable) {  in intel_get_load_detect_pipe()
6638 			drm_modeset_unlock(&possible_crtc->base.mutex);  in intel_get_load_detect_pipe()
6650 		drm_dbg_kms(&dev_priv->drm,  in intel_get_load_detect_pipe()
6651 			    "no pipe available for load-detect\n");  in intel_get_load_detect_pipe()
6652 		ret = -ENODEV;  in intel_get_load_detect_pipe()
6660 		ret = -ENOMEM;  in intel_get_load_detect_pipe()
6664 	state->acquire_ctx = ctx;  in intel_get_load_detect_pipe()
6665 	restore_state->acquire_ctx = ctx;  in intel_get_load_detect_pipe()
6673 	ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);  in intel_get_load_detect_pipe()
6683 	crtc_state->uapi.active = true;  in intel_get_load_detect_pipe()
6685 	ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,  in intel_get_load_detect_pipe()
6690 	ret = intel_modeset_disable_planes(state, &crtc->base);  in intel_get_load_detect_pipe()
6696 		ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));  in intel_get_load_detect_pipe()
6698 		ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);  in intel_get_load_detect_pipe()
6700 		drm_dbg_kms(&dev_priv->drm,  in intel_get_load_detect_pipe()
6708 		drm_dbg_kms(&dev_priv->drm,  in intel_get_load_detect_pipe()
6709 			    "failed to set mode on load-detect pipe\n");  in intel_get_load_detect_pipe()
6713 	old->restore_state = restore_state;  in intel_get_load_detect_pipe()
6717 	intel_wait_for_vblank(dev_priv, crtc->pipe);  in intel_get_load_detect_pipe()
6730 	if (ret == -EDEADLK)  in intel_get_load_detect_pipe()
6742 	struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);  in intel_release_load_detect_pipe()
6743 	struct drm_encoder *encoder = &intel_encoder->base;  in intel_release_load_detect_pipe()
6744 	struct drm_atomic_state *state = old->restore_state;  in intel_release_load_detect_pipe()
6747 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",  in intel_release_load_detect_pipe()
6748 		    connector->base.id, connector->name,  in intel_release_load_detect_pipe()
6749 		    encoder->base.id, encoder->name);  in intel_release_load_detect_pipe()
6756 		drm_dbg_kms(&i915->drm,  in intel_release_load_detect_pipe()
6765 	u32 dpll = pipe_config->dpll_hw_state.dpll;  in i9xx_pll_refclk()
6768 		return dev_priv->vbt.lvds_ssc_freq;  in i9xx_pll_refclk()
6781 	struct drm_device *dev = crtc->base.dev;  in i9xx_crtc_clock_get()
6783 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_clock_get()
6784 	u32 dpll = pipe_config->dpll_hw_state.dpll;  in i9xx_crtc_clock_get()
6791 		fp = pipe_config->dpll_hw_state.fp0;  in i9xx_crtc_clock_get()
6793 		fp = pipe_config->dpll_hw_state.fp1;  in i9xx_crtc_clock_get()
6797 		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;  in i9xx_crtc_clock_get()
6822 			drm_dbg_kms(&dev_priv->drm,  in i9xx_crtc_clock_get()
6866 	pipe_config->port_clock = port_clock;  in i9xx_crtc_clock_get()
6882 	if (!m_n->link_n)  in intel_dotclock_calculate()
6885 	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);  in intel_dotclock_calculate()
6891 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pch_clock_get()
6901 	pipe_config->hw.adjusted_mode.crtc_clock =  in ilk_pch_clock_get()
6903 					 &pipe_config->fdi_m_n);  in ilk_pch_clock_get()
6910 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_encoder_current_mode()
6916 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
6939 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
6947  * intel_wm_need_update - Check whether watermarks need updating
6960 	if (new->uapi.visible != cur->uapi.visible)  in intel_wm_need_update()
6963 	if (!cur->hw.fb || !new->hw.fb)  in intel_wm_need_update()
6966 	if (cur->hw.fb->modifier != new->hw.fb->modifier ||  in intel_wm_need_update()
6967 	    cur->hw.rotation != new->hw.rotation ||  in intel_wm_need_update()
6968 	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||  in intel_wm_need_update()
6969 	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||  in intel_wm_need_update()
6970 	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||  in intel_wm_need_update()
6971 	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))  in intel_wm_need_update()
6979 	int src_w = drm_rect_width(&state->uapi.src) >> 16;  in needs_scaling()
6980 	int src_h = drm_rect_height(&state->uapi.src) >> 16;  in needs_scaling()
6981 	int dst_w = drm_rect_width(&state->uapi.dst);  in needs_scaling()
6982 	int dst_h = drm_rect_height(&state->uapi.dst);  in needs_scaling()
6992 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_plane_atomic_calc_changes()
6993 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_atomic_calc_changes()
6994 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_atomic_calc_changes()
6996 	bool was_crtc_enabled = old_crtc_state->hw.active;  in intel_plane_atomic_calc_changes()
6997 	bool is_crtc_enabled = crtc_state->hw.active;  in intel_plane_atomic_calc_changes()
7001 	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {  in intel_plane_atomic_calc_changes()
7007 	was_visible = old_plane_state->uapi.visible;  in intel_plane_atomic_calc_changes()
7008 	visible = plane_state->uapi.visible;  in intel_plane_atomic_calc_changes()
7010 	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))  in intel_plane_atomic_calc_changes()
7020 	 * per-plane wm computation to the .check_plane() hook, and  in intel_plane_atomic_calc_changes()
7034 	drm_dbg_atomic(&dev_priv->drm,  in intel_plane_atomic_calc_changes()
7035 		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",  in intel_plane_atomic_calc_changes()
7036 		       crtc->base.base.id, crtc->base.name,  in intel_plane_atomic_calc_changes()
7037 		       plane->base.base.id, plane->base.name,  in intel_plane_atomic_calc_changes()
7043 			crtc_state->update_wm_pre = true;  in intel_plane_atomic_calc_changes()
7046 		if (plane->id != PLANE_CURSOR)  in intel_plane_atomic_calc_changes()
7047 			crtc_state->disable_cxsr = true;  in intel_plane_atomic_calc_changes()
7050 			crtc_state->update_wm_post = true;  in intel_plane_atomic_calc_changes()
7053 		if (plane->id != PLANE_CURSOR)  in intel_plane_atomic_calc_changes()
7054 			crtc_state->disable_cxsr = true;  in intel_plane_atomic_calc_changes()
7058 			crtc_state->update_wm_pre = true;  in intel_plane_atomic_calc_changes()
7059 			crtc_state->update_wm_post = true;  in intel_plane_atomic_calc_changes()
7064 		crtc_state->fb_bits |= plane->frontbuffer_bit;  in intel_plane_atomic_calc_changes()
7099 	if (plane->id != PLANE_CURSOR &&  in intel_plane_atomic_calc_changes()
7104 		crtc_state->disable_lp_wm = true;  in intel_plane_atomic_calc_changes()
7113 	return a == b || (a->cloneable & (1 << b->type) &&  in encoders_cloneable()
7114 			  b->cloneable & (1 << a->type));  in encoders_cloneable()
7126 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
7127 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
7131 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
7146 		linked = plane_state->planar_linked_plane;  in icl_add_linked_planes()
7155 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
7156 			    linked_plane_state->planar_linked_plane != plane);  in icl_add_linked_planes()
7157 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
7158 			    linked_plane_state->planar_slave == plane_state->planar_slave);  in icl_add_linked_planes()
7166 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_check_nv12_planes()
7167 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_check_nv12_planes()
7168 	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);  in icl_check_nv12_planes()
7178 	 * in the crtc_state->active_planes mask.  in icl_check_nv12_planes()
7181 		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)  in icl_check_nv12_planes()
7184 		plane_state->planar_linked_plane = NULL;  in icl_check_nv12_planes()
7185 		if (plane_state->planar_slave && !plane_state->uapi.visible) {  in icl_check_nv12_planes()
7186 			crtc_state->enabled_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
7187 			crtc_state->active_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
7188 			crtc_state->update_planes |= BIT(plane->id);  in icl_check_nv12_planes()
7191 		plane_state->planar_slave = false;  in icl_check_nv12_planes()
7194 	if (!crtc_state->nv12_planes)  in icl_check_nv12_planes()
7200 		if (plane->pipe != crtc->pipe ||  in icl_check_nv12_planes()
7201 		    !(crtc_state->nv12_planes & BIT(plane->id)))  in icl_check_nv12_planes()
7204 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {  in icl_check_nv12_planes()
7205 			if (!icl_is_nv12_y_plane(dev_priv, linked->id))  in icl_check_nv12_planes()
7208 			if (crtc_state->active_planes & BIT(linked->id))  in icl_check_nv12_planes()
7219 			drm_dbg_kms(&dev_priv->drm,  in icl_check_nv12_planes()
7221 				    hweight8(crtc_state->nv12_planes));  in icl_check_nv12_planes()
7223 			return -EINVAL;  in icl_check_nv12_planes()
7226 		plane_state->planar_linked_plane = linked;  in icl_check_nv12_planes()
7228 		linked_state->planar_slave = true;  in icl_check_nv12_planes()
7229 		linked_state->planar_linked_plane = plane;  in icl_check_nv12_planes()
7230 		crtc_state->enabled_planes |= BIT(linked->id);  in icl_check_nv12_planes()
7231 		crtc_state->active_planes |= BIT(linked->id);  in icl_check_nv12_planes()
7232 		crtc_state->update_planes |= BIT(linked->id);  in icl_check_nv12_planes()
7233 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",  in icl_check_nv12_planes()
7234 			    linked->base.name, plane->base.name);  in icl_check_nv12_planes()
7237 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;  in icl_check_nv12_planes()
7238 		linked_state->color_ctl = plane_state->color_ctl;  in icl_check_nv12_planes()
7239 		linked_state->view = plane_state->view;  in icl_check_nv12_planes()
7242 		linked_state->uapi.src = plane_state->uapi.src;  in icl_check_nv12_planes()
7243 		linked_state->uapi.dst = plane_state->uapi.dst;  in icl_check_nv12_planes()
7245 		if (icl_is_hdr_plane(dev_priv, plane->id)) {  in icl_check_nv12_planes()
7246 			if (linked->id == PLANE_SPRITE5)  in icl_check_nv12_planes()
7247 				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;  in icl_check_nv12_planes()
7248 			else if (linked->id == PLANE_SPRITE4)  in icl_check_nv12_planes()
7249 				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;  in icl_check_nv12_planes()
7250 			else if (linked->id == PLANE_SPRITE3)  in icl_check_nv12_planes()
7251 				plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;  in icl_check_nv12_planes()
7252 			else if (linked->id == PLANE_SPRITE2)  in icl_check_nv12_planes()
7253 				plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;  in icl_check_nv12_planes()
7255 				MISSING_CASE(linked->id);  in icl_check_nv12_planes()
7264 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in c8_planes_changed()
7266 		to_intel_atomic_state(new_crtc_state->uapi.state);  in c8_planes_changed()
7270 	return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;  in c8_planes_changed()
7276 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
7279 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
7282 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
7283 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
7292 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
7295 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
7298 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
7299 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
7306 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_linetime_wm()
7307 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_linetime_wm()
7309 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
7312 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
7315 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
7316 				   crtc_state->pixel_rate);  in skl_linetime_wm()
7320 	    dev_priv->ipc_enabled)  in skl_linetime_wm()
7329 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_compute_linetime_wm()
7335 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
7337 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
7346 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
7355 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_atomic_check()
7362 	    mode_changed && !crtc_state->hw.active)  in intel_crtc_atomic_check()
7363 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
7365 	if (mode_changed && crtc_state->hw.enable &&  in intel_crtc_atomic_check()
7366 	    dev_priv->display.crtc_compute_clock &&  in intel_crtc_atomic_check()
7367 	    !crtc_state->bigjoiner_slave &&  in intel_crtc_atomic_check()
7368 	    !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {  in intel_crtc_atomic_check()
7369 		ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);  in intel_crtc_atomic_check()
7379 		crtc_state->uapi.color_mgmt_changed = true;  in intel_crtc_atomic_check()
7381 	if (mode_changed || crtc_state->update_pipe ||  in intel_crtc_atomic_check()
7382 	    crtc_state->uapi.color_mgmt_changed) {  in intel_crtc_atomic_check()
7388 	if (dev_priv->display.compute_pipe_wm) {  in intel_crtc_atomic_check()
7389 		ret = dev_priv->display.compute_pipe_wm(state, crtc);  in intel_crtc_atomic_check()
7391 			drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
7398 	if (dev_priv->display.compute_intermediate_wm) {  in intel_crtc_atomic_check()
7399 		if (drm_WARN_ON(&dev_priv->drm,  in intel_crtc_atomic_check()
7400 				!dev_priv->display.compute_pipe_wm))  in intel_crtc_atomic_check()
7408 		ret = dev_priv->display.compute_intermediate_wm(state, crtc);  in intel_crtc_atomic_check()
7410 			drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
7417 		if (mode_changed || crtc_state->update_pipe) {  in intel_crtc_atomic_check()
7458 		struct drm_connector_state *conn_state = connector->base.state;  in intel_modeset_update_connector_atomic_state()
7460 			to_intel_encoder(connector->base.encoder);  in intel_modeset_update_connector_atomic_state()
7462 		if (conn_state->crtc)  in intel_modeset_update_connector_atomic_state()
7463 			drm_connector_put(&connector->base);  in intel_modeset_update_connector_atomic_state()
7467 				to_intel_crtc(encoder->base.crtc);  in intel_modeset_update_connector_atomic_state()
7469 				to_intel_crtc_state(crtc->base.state);  in intel_modeset_update_connector_atomic_state()
7471 			conn_state->best_encoder = &encoder->base;  in intel_modeset_update_connector_atomic_state()
7472 			conn_state->crtc = &crtc->base;  in intel_modeset_update_connector_atomic_state()
7473 			conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;  in intel_modeset_update_connector_atomic_state()
7475 			drm_connector_get(&connector->base);  in intel_modeset_update_connector_atomic_state()
7477 			conn_state->best_encoder = NULL;  in intel_modeset_update_connector_atomic_state()
7478 			conn_state->crtc = NULL;  in intel_modeset_update_connector_atomic_state()
7488 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
7489 	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);  in compute_sink_pipe_bpp()
7490 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
7493 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
7507 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
7508 		return -EINVAL;  in compute_sink_pipe_bpp()
7511 	if (bpp < pipe_config->pipe_bpp) {  in compute_sink_pipe_bpp()
7512 		drm_dbg_kms(&i915->drm,  in compute_sink_pipe_bpp()
7515 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
7516 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
7517 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
7518 			    pipe_config->pipe_bpp);  in compute_sink_pipe_bpp()
7520 		pipe_config->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
7530 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in compute_baseline_pipe_bpp()
7531 	struct drm_atomic_state *state = pipe_config->uapi.state;  in compute_baseline_pipe_bpp()
7544 	pipe_config->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
7550 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
7564 	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "  in intel_dump_crtc_timings()
7566 		    mode->crtc_clock,  in intel_dump_crtc_timings()
7567 		    mode->crtc_hdisplay, mode->crtc_hsync_start,  in intel_dump_crtc_timings()
7568 		    mode->crtc_hsync_end, mode->crtc_htotal,  in intel_dump_crtc_timings()
7569 		    mode->crtc_vdisplay, mode->crtc_vsync_start,  in intel_dump_crtc_timings()
7570 		    mode->crtc_vsync_end, mode->crtc_vtotal,  in intel_dump_crtc_timings()
7571 		    mode->type, mode->flags);  in intel_dump_crtc_timings()
7579 	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);  in intel_dump_m_n_config()
7581 	drm_dbg_kms(&i915->drm,  in intel_dump_m_n_config()
7584 		    m_n->gmch_m, m_n->gmch_n,  in intel_dump_m_n_config()
7585 		    m_n->link_m, m_n->link_n, m_n->tu);  in intel_dump_m_n_config()
7595 	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);  in intel_dump_infoframe()
7605 	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);  in intel_dump_dp_vsc_sdp()
7646 		len -= r;  in snprintf_output_types()
7669 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_dump_plane_state()
7670 	struct drm_i915_private *i915 = to_i915(plane->base.dev);  in intel_dump_plane_state()
7671 	const struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_dump_plane_state()
7674 		drm_dbg_kms(&i915->drm,  in intel_dump_plane_state()
7676 			    plane->base.base.id, plane->base.name,  in intel_dump_plane_state()
7677 			    yesno(plane_state->uapi.visible));  in intel_dump_plane_state()
7681 	drm_dbg_kms(&i915->drm,  in intel_dump_plane_state()
7683 		    plane->base.base.id, plane->base.name,  in intel_dump_plane_state()
7684 		    fb->base.id, fb->width, fb->height, &fb->format->format,  in intel_dump_plane_state()
7685 		    fb->modifier, yesno(plane_state->uapi.visible));  in intel_dump_plane_state()
7686 	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",  in intel_dump_plane_state()
7687 		    plane_state->hw.rotation, plane_state->scaler_id);  in intel_dump_plane_state()
7688 	if (plane_state->uapi.visible)  in intel_dump_plane_state()
7689 		drm_dbg_kms(&i915->drm,  in intel_dump_plane_state()
7691 			    DRM_RECT_FP_ARG(&plane_state->uapi.src),  in intel_dump_plane_state()
7692 			    DRM_RECT_ARG(&plane_state->uapi.dst));  in intel_dump_plane_state()
7699 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dump_pipe_config()
7700 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_dump_pipe_config()
7706 	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",  in intel_dump_pipe_config()
7707 		    crtc->base.base.id, crtc->base.name,  in intel_dump_pipe_config()
7708 		    yesno(pipe_config->hw.enable), context);  in intel_dump_pipe_config()
7710 	if (!pipe_config->hw.enable)  in intel_dump_pipe_config()
7713 	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);  in intel_dump_pipe_config()
7714 	drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7716 		    yesno(pipe_config->hw.active),  in intel_dump_pipe_config()
7717 		    buf, pipe_config->output_types,  in intel_dump_pipe_config()
7718 		    output_formats(pipe_config->output_format));  in intel_dump_pipe_config()
7720 	drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7722 		    transcoder_name(pipe_config->cpu_transcoder),  in intel_dump_pipe_config()
7723 		    pipe_config->pipe_bpp, pipe_config->dither);  in intel_dump_pipe_config()
7725 	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",  in intel_dump_pipe_config()
7726 		    transcoder_name(pipe_config->mst_master_transcoder));  in intel_dump_pipe_config()
7728 	drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7730 		    transcoder_name(pipe_config->master_transcoder),  in intel_dump_pipe_config()
7731 		    pipe_config->sync_mode_slaves_mask);  in intel_dump_pipe_config()
7733 	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",  in intel_dump_pipe_config()
7734 		    pipe_config->bigjoiner_slave ? "slave" :  in intel_dump_pipe_config()
7735 		    pipe_config->bigjoiner ? "master" : "no");  in intel_dump_pipe_config()
7737 	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",  in intel_dump_pipe_config()
7738 		    enableddisabled(pipe_config->splitter.enable),  in intel_dump_pipe_config()
7739 		    pipe_config->splitter.link_count,  in intel_dump_pipe_config()
7740 		    pipe_config->splitter.pixel_overlap);  in intel_dump_pipe_config()
7742 	if (pipe_config->has_pch_encoder)  in intel_dump_pipe_config()
7744 				      pipe_config->fdi_lanes,  in intel_dump_pipe_config()
7745 				      &pipe_config->fdi_m_n);  in intel_dump_pipe_config()
7749 				pipe_config->lane_count, &pipe_config->dp_m_n);  in intel_dump_pipe_config()
7750 		if (pipe_config->has_drrs)  in intel_dump_pipe_config()
7752 					      pipe_config->lane_count,  in intel_dump_pipe_config()
7753 					      &pipe_config->dp_m2_n2);  in intel_dump_pipe_config()
7756 	drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7758 		    pipe_config->has_audio, pipe_config->has_infoframe,  in intel_dump_pipe_config()
7759 		    pipe_config->infoframes.enable);  in intel_dump_pipe_config()
7761 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7763 		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",  in intel_dump_pipe_config()
7764 			    pipe_config->infoframes.gcp);  in intel_dump_pipe_config()
7765 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7767 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);  in intel_dump_pipe_config()
7768 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7770 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);  in intel_dump_pipe_config()
7771 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7773 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);  in intel_dump_pipe_config()
7774 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7776 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);  in intel_dump_pipe_config()
7777 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7779 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);  in intel_dump_pipe_config()
7780 	if (pipe_config->infoframes.enable &  in intel_dump_pipe_config()
7782 		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);  in intel_dump_pipe_config()
7784 …drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d fliplin…  in intel_dump_pipe_config()
7785 		    yesno(pipe_config->vrr.enable),  in intel_dump_pipe_config()
7786 		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,  in intel_dump_pipe_config()
7787 		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,  in intel_dump_pipe_config()
7788 		    pipe_config->vrr.flipline,  in intel_dump_pipe_config()
7792 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");  in intel_dump_pipe_config()
7793 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);  in intel_dump_pipe_config()
7794 	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");  in intel_dump_pipe_config()
7795 	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);  in intel_dump_pipe_config()
7796 	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);  in intel_dump_pipe_config()
7797 	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");  in intel_dump_pipe_config()
7798 	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);  in intel_dump_pipe_config()
7799 	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);  in intel_dump_pipe_config()
7800 	drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7802 		    pipe_config->port_clock,  in intel_dump_pipe_config()
7803 		    pipe_config->pipe_src_w, pipe_config->pipe_src_h,  in intel_dump_pipe_config()
7804 		    pipe_config->pixel_rate);  in intel_dump_pipe_config()
7806 	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",  in intel_dump_pipe_config()
7807 		    pipe_config->linetime, pipe_config->ips_linetime);  in intel_dump_pipe_config()
7810 		drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7812 			    crtc->num_scalers,  in intel_dump_pipe_config()
7813 			    pipe_config->scaler_state.scaler_users,  in intel_dump_pipe_config()
7814 			    pipe_config->scaler_state.scaler_id);  in intel_dump_pipe_config()
7817 		drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7819 			    pipe_config->gmch_pfit.control,  in intel_dump_pipe_config()
7820 			    pipe_config->gmch_pfit.pgm_ratios,  in intel_dump_pipe_config()
7821 			    pipe_config->gmch_pfit.lvds_border_bits);  in intel_dump_pipe_config()
7823 		drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7825 			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),  in intel_dump_pipe_config()
7826 			    enableddisabled(pipe_config->pch_pfit.enabled),  in intel_dump_pipe_config()
7827 			    yesno(pipe_config->pch_pfit.force_thru));  in intel_dump_pipe_config()
7829 	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",  in intel_dump_pipe_config()
7830 		    pipe_config->ips_enabled, pipe_config->double_wide);  in intel_dump_pipe_config()
7832 	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);  in intel_dump_pipe_config()
7835 		drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7837 			    pipe_config->cgm_mode, pipe_config->gamma_mode,  in intel_dump_pipe_config()
7838 			    pipe_config->gamma_enable, pipe_config->csc_enable);  in intel_dump_pipe_config()
7840 		drm_dbg_kms(&dev_priv->drm,  in intel_dump_pipe_config()
7842 			    pipe_config->csc_mode, pipe_config->gamma_mode,  in intel_dump_pipe_config()
7843 			    pipe_config->gamma_enable, pipe_config->csc_enable);  in intel_dump_pipe_config()
7845 	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",  in intel_dump_pipe_config()
7846 		    pipe_config->hw.degamma_lut ?  in intel_dump_pipe_config()
7847 		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,  in intel_dump_pipe_config()
7848 		    pipe_config->hw.gamma_lut ?  in intel_dump_pipe_config()
7849 		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);  in intel_dump_pipe_config()
7856 		if (plane->pipe == crtc->pipe)  in intel_dump_pipe_config()
7863 	struct drm_device *dev = state->base.dev;  in check_digital_port_conflicts()
7871 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
7874 	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);  in check_digital_port_conflicts()
7887 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
7890 			connector_state = connector->state;  in check_digital_port_conflicts()
7892 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
7895 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
7897 		drm_WARN_ON(dev, !connector_state->crtc);  in check_digital_port_conflicts()
7899 		switch (encoder->type) {  in check_digital_port_conflicts()
7908 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
7911 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
7915 				1 << encoder->port;  in check_digital_port_conflicts()
7936 	if (crtc_state->bigjoiner_slave) {  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
7938 								  crtc_state->bigjoiner_linked_crtc);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
7952 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state()
7953 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state()
7954 	crtc_state->hw.mode = crtc_state->uapi.mode;  in intel_crtc_copy_uapi_to_hw_state()
7955 	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;  in intel_crtc_copy_uapi_to_hw_state()
7956 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state()
7963 	if (crtc_state->bigjoiner_slave)  in intel_crtc_copy_hw_to_uapi_state()
7966 	crtc_state->uapi.enable = crtc_state->hw.enable;  in intel_crtc_copy_hw_to_uapi_state()
7967 	crtc_state->uapi.active = crtc_state->hw.active;  in intel_crtc_copy_hw_to_uapi_state()
7968 	drm_WARN_ON(crtc_state->uapi.crtc->dev,  in intel_crtc_copy_hw_to_uapi_state()
7969 		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);  in intel_crtc_copy_hw_to_uapi_state()
7971 	crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;  in intel_crtc_copy_hw_to_uapi_state()
7972 	crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;  in intel_crtc_copy_hw_to_uapi_state()
7975 	drm_property_replace_blob(&crtc_state->uapi.degamma_lut,  in intel_crtc_copy_hw_to_uapi_state()
7976 				  crtc_state->hw.degamma_lut);  in intel_crtc_copy_hw_to_uapi_state()
7977 	drm_property_replace_blob(&crtc_state->uapi.gamma_lut,  in intel_crtc_copy_hw_to_uapi_state()
7978 				  crtc_state->hw.gamma_lut);  in intel_crtc_copy_hw_to_uapi_state()
7979 	drm_property_replace_blob(&crtc_state->uapi.ctm,  in intel_crtc_copy_hw_to_uapi_state()
7980 				  crtc_state->hw.ctm);  in intel_crtc_copy_hw_to_uapi_state()
7988 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in copy_bigjoiner_crtc_state()
7992 		return -ENOMEM;  in copy_bigjoiner_crtc_state()
7994 	saved_state->uapi = crtc_state->uapi;  in copy_bigjoiner_crtc_state()
7995 	saved_state->scaler_state = crtc_state->scaler_state;  in copy_bigjoiner_crtc_state()
7996 	saved_state->shared_dpll = crtc_state->shared_dpll;  in copy_bigjoiner_crtc_state()
7997 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in copy_bigjoiner_crtc_state()
7998 	saved_state->crc_enabled = crtc_state->crc_enabled;  in copy_bigjoiner_crtc_state()
8004 	/* Re-init hw state */  in copy_bigjoiner_crtc_state()
8005 	memset(&crtc_state->hw, 0, sizeof(saved_state->hw));  in copy_bigjoiner_crtc_state()
8006 	crtc_state->hw.enable = from_crtc_state->hw.enable;  in copy_bigjoiner_crtc_state()
8007 	crtc_state->hw.active = from_crtc_state->hw.active;  in copy_bigjoiner_crtc_state()
8008 	crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;  in copy_bigjoiner_crtc_state()
8009 	crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;  in copy_bigjoiner_crtc_state()
8012 	crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;  in copy_bigjoiner_crtc_state()
8013 	crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;  in copy_bigjoiner_crtc_state()
8014 	crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;  in copy_bigjoiner_crtc_state()
8015 	crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;  in copy_bigjoiner_crtc_state()
8016 	crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);  in copy_bigjoiner_crtc_state()
8017 	crtc_state->bigjoiner_slave = true;  in copy_bigjoiner_crtc_state()
8018 	crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;  in copy_bigjoiner_crtc_state()
8019 	crtc_state->has_audio = false;  in copy_bigjoiner_crtc_state()
8028 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_prepare_cleared_state()
8029 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_prepare_cleared_state()
8034 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
8036 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
8044 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
8045 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
8046 	saved_state->shared_dpll = crtc_state->shared_dpll;  in intel_crtc_prepare_cleared_state()
8047 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
8048 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
8049 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
8050 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
8053 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
8067 	struct drm_crtc *crtc = pipe_config->uapi.crtc;  in intel_modeset_pipe_config()
8068 	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);  in intel_modeset_pipe_config()
8074 	pipe_config->cpu_transcoder =  in intel_modeset_pipe_config()
8075 		(enum transcoder) to_intel_crtc(crtc)->pipe;  in intel_modeset_pipe_config()
8082 	if (!(pipe_config->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
8084 		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
8086 	if (!(pipe_config->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
8088 		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
8095 	base_bpp = pipe_config->pipe_bpp;  in intel_modeset_pipe_config()
8105 	drm_mode_get_hv_timing(&pipe_config->hw.mode,  in intel_modeset_pipe_config()
8106 			       &pipe_config->pipe_src_w,  in intel_modeset_pipe_config()
8107 			       &pipe_config->pipe_src_h);  in intel_modeset_pipe_config()
8109 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
8111 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
8113 		if (connector_state->crtc != crtc)  in intel_modeset_pipe_config()
8117 			drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
8119 			return -EINVAL;  in intel_modeset_pipe_config()
8126 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
8127 			pipe_config->output_types |=  in intel_modeset_pipe_config()
8128 				BIT(encoder->compute_output_type(encoder, pipe_config,  in intel_modeset_pipe_config()
8131 			pipe_config->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
8136 	pipe_config->port_clock = 0;  in intel_modeset_pipe_config()
8137 	pipe_config->pixel_multiplier = 1;  in intel_modeset_pipe_config()
8140 	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,  in intel_modeset_pipe_config()
8147 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
8149 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
8151 		if (connector_state->crtc != crtc)  in intel_modeset_pipe_config()
8154 		ret = encoder->compute_config(encoder, pipe_config,  in intel_modeset_pipe_config()
8157 			if (ret != -EDEADLK)  in intel_modeset_pipe_config()
8158 				drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
8167 	if (!pipe_config->port_clock)  in intel_modeset_pipe_config()
8168 		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
8169 			* pipe_config->pixel_multiplier;  in intel_modeset_pipe_config()
8172 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
8175 		drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");  in intel_modeset_pipe_config()
8180 		if (drm_WARN(&i915->drm, !retry,  in intel_modeset_pipe_config()
8182 			return -EINVAL;  in intel_modeset_pipe_config()
8184 		drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");  in intel_modeset_pipe_config()
8189 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
8193 	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
8194 		!pipe_config->dither_force_disable;  in intel_modeset_pipe_config()
8195 	drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
8197 		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);  in intel_modeset_pipe_config()
8206 		to_intel_atomic_state(crtc_state->uapi.state);  in intel_modeset_pipe_config_late()
8207 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe_config_late()
8212 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
8215 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
8218 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
8219 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
8222 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
8241 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
8285 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
8286 		intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,  in intel_compare_link_m_n()
8287 				  m2_n2->gmch_m, m2_n2->gmch_n, exact) &&  in intel_compare_link_m_n()
8288 		intel_compare_m_n(m_n->link_m, m_n->link_n,  in intel_compare_link_m_n()
8289 				  m2_n2->link_m, m2_n2->link_n, exact);  in intel_compare_link_m_n()
8316 		drm_dbg_kms(&dev_priv->drm,  in pipe_config_infoframe_mismatch()
8318 		drm_dbg_kms(&dev_priv->drm, "expected:\n");  in pipe_config_infoframe_mismatch()
8319 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);  in pipe_config_infoframe_mismatch()
8320 		drm_dbg_kms(&dev_priv->drm, "found:\n");  in pipe_config_infoframe_mismatch()
8321 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);  in pipe_config_infoframe_mismatch()
8323 		drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);  in pipe_config_infoframe_mismatch()
8324 		drm_err(&dev_priv->drm, "expected:\n");  in pipe_config_infoframe_mismatch()
8325 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);  in pipe_config_infoframe_mismatch()
8326 		drm_err(&dev_priv->drm, "found:\n");  in pipe_config_infoframe_mismatch()
8327 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);  in pipe_config_infoframe_mismatch()
8341 		drm_dbg_kms(&dev_priv->drm,  in pipe_config_dp_vsc_sdp_mismatch()
8343 		drm_dbg_kms(&dev_priv->drm, "expected:\n");  in pipe_config_dp_vsc_sdp_mismatch()
8344 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);  in pipe_config_dp_vsc_sdp_mismatch()
8345 		drm_dbg_kms(&dev_priv->drm, "found:\n");  in pipe_config_dp_vsc_sdp_mismatch()
8346 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);  in pipe_config_dp_vsc_sdp_mismatch()
8348 		drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);  in pipe_config_dp_vsc_sdp_mismatch()
8349 		drm_err(&dev_priv->drm, "expected:\n");  in pipe_config_dp_vsc_sdp_mismatch()
8350 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);  in pipe_config_dp_vsc_sdp_mismatch()
8351 		drm_err(&dev_priv->drm, "found:\n");  in pipe_config_dp_vsc_sdp_mismatch()
8352 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);  in pipe_config_dp_vsc_sdp_mismatch()
8360 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_mismatch()
8369 		drm_dbg_kms(&i915->drm,  in pipe_config_mismatch()
8371 			    crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
8373 		drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",  in pipe_config_mismatch()
8374 			crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
8381 	if (dev_priv->params.fastboot != -1)  in fastboot_enabled()
8382 		return dev_priv->params.fastboot;  in fastboot_enabled()
8401 	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);  in intel_pipe_config_compare()
8402 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
8406 		current_config->inherited && !pipe_config->inherited;  in intel_pipe_config_compare()
8409 		drm_dbg_kms(&dev_priv->drm,  in intel_pipe_config_compare()
8415 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
8418 				     current_config->name, \  in intel_pipe_config_compare()
8419 				     pipe_config->name); \  in intel_pipe_config_compare()
8425 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
8428 				     current_config->name & (mask), \  in intel_pipe_config_compare()
8429 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
8435 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
8438 				     current_config->name, \  in intel_pipe_config_compare()
8439 				     pipe_config->name); \  in intel_pipe_config_compare()
8445 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
8448 				     yesno(current_config->name), \  in intel_pipe_config_compare()
8449 				     yesno(pipe_config->name)); \  in intel_pipe_config_compare()
8460 	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \  in intel_pipe_config_compare()
8465 				     yesno(current_config->name), \  in intel_pipe_config_compare()
8466 				     yesno(pipe_config->name)); \  in intel_pipe_config_compare()
8472 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
8475 				     current_config->name, \  in intel_pipe_config_compare()
8476 				     pipe_config->name); \  in intel_pipe_config_compare()
8482 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
8483 				    &pipe_config->name,\  in intel_pipe_config_compare()
8488 				     current_config->name.tu, \  in intel_pipe_config_compare()
8489 				     current_config->name.gmch_m, \  in intel_pipe_config_compare()
8490 				     current_config->name.gmch_n, \  in intel_pipe_config_compare()
8491 				     current_config->name.link_m, \  in intel_pipe_config_compare()
8492 				     current_config->name.link_n, \  in intel_pipe_config_compare()
8493 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
8494 				     pipe_config->name.gmch_m, \  in intel_pipe_config_compare()
8495 				     pipe_config->name.gmch_n, \  in intel_pipe_config_compare()
8496 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
8497 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
8508 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
8509 				    &pipe_config->name, !fastset) && \  in intel_pipe_config_compare()
8510 	    !intel_compare_link_m_n(&current_config->alt_name, \  in intel_pipe_config_compare()
8511 				    &pipe_config->name, !fastset)) { \  in intel_pipe_config_compare()
8516 				     current_config->name.tu, \  in intel_pipe_config_compare()
8517 				     current_config->name.gmch_m, \  in intel_pipe_config_compare()
8518 				     current_config->name.gmch_n, \  in intel_pipe_config_compare()
8519 				     current_config->name.link_m, \  in intel_pipe_config_compare()
8520 				     current_config->name.link_n, \  in intel_pipe_config_compare()
8521 				     current_config->alt_name.tu, \  in intel_pipe_config_compare()
8522 				     current_config->alt_name.gmch_m, \  in intel_pipe_config_compare()
8523 				     current_config->alt_name.gmch_n, \  in intel_pipe_config_compare()
8524 				     current_config->alt_name.link_m, \  in intel_pipe_config_compare()
8525 				     current_config->alt_name.link_n, \  in intel_pipe_config_compare()
8526 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
8527 				     pipe_config->name.gmch_m, \  in intel_pipe_config_compare()
8528 				     pipe_config->name.gmch_n, \  in intel_pipe_config_compare()
8529 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
8530 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
8536 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
8540 				     current_config->name & (mask), \  in intel_pipe_config_compare()
8541 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
8547 	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \  in intel_pipe_config_compare()
8550 				     current_config->name, \  in intel_pipe_config_compare()
8551 				     pipe_config->name); \  in intel_pipe_config_compare()
8557 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
8558 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
8560 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
8561 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
8567 	if (!current_config->has_psr && !pipe_config->has_psr && \  in intel_pipe_config_compare()
8568 	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
8569 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
8571 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
8572 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
8578 	if (current_config->name1 != pipe_config->name1) { \  in intel_pipe_config_compare()
8581 				current_config->name1, \  in intel_pipe_config_compare()
8582 				pipe_config->name1); \  in intel_pipe_config_compare()
8585 		if (!intel_color_lut_equal(current_config->name2, \  in intel_pipe_config_compare()
8586 					pipe_config->name2, pipe_config->name1, \  in intel_pipe_config_compare()
8596 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
8610 		if (current_config->has_drrs)  in intel_pipe_config_compare()
8696 		if (current_config->pch_pfit.enabled) {  in intel_pipe_config_compare()
8731 	if (dev_priv->dpll.mgr)  in intel_pipe_config_compare()
8735 	if (dev_priv->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {  in intel_pipe_config_compare()
8783 	if (fastset && (current_config->has_psr || pipe_config->has_psr))  in intel_pipe_config_compare()
8835 	if (pipe_config->has_pch_encoder) {  in intel_pipe_config_sanity_check()
8837 							    &pipe_config->fdi_m_n);  in intel_pipe_config_sanity_check()
8838 		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;  in intel_pipe_config_sanity_check()
8844 		drm_WARN(&dev_priv->drm,  in intel_pipe_config_sanity_check()
8854 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in verify_wm_state()
8860 	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;  in verify_wm_state()
8865 	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)  in verify_wm_state()
8872 	skl_pipe_wm_get_hw_state(crtc, &hw->wm);  in verify_wm_state()
8874 	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);  in verify_wm_state()
8879 	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)  in verify_wm_state()
8880 		drm_err(&dev_priv->drm,  in verify_wm_state()
8882 			dev_priv->dbuf.enabled_slices,  in verify_wm_state()
8885 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in verify_wm_state()
8891 			hw_wm_level = &hw->wm.planes[plane->id].wm[level];  in verify_wm_state()
8892 			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);  in verify_wm_state()
8897 			drm_err(&dev_priv->drm,  in verify_wm_state()
8899 				plane->base.base.id, plane->base.name, level,  in verify_wm_state()
8900 				sw_wm_level->enable,  in verify_wm_state()
8901 				sw_wm_level->blocks,  in verify_wm_state()
8902 				sw_wm_level->lines,  in verify_wm_state()
8903 				hw_wm_level->enable,  in verify_wm_state()
8904 				hw_wm_level->blocks,  in verify_wm_state()
8905 				hw_wm_level->lines);  in verify_wm_state()
8908 		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;  in verify_wm_state()
8909 		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);  in verify_wm_state()
8912 			drm_err(&dev_priv->drm,  in verify_wm_state()
8914 				plane->base.base.id, plane->base.name,  in verify_wm_state()
8915 				sw_wm_level->enable,  in verify_wm_state()
8916 				sw_wm_level->blocks,  in verify_wm_state()
8917 				sw_wm_level->lines,  in verify_wm_state()
8918 				hw_wm_level->enable,  in verify_wm_state()
8919 				hw_wm_level->blocks,  in verify_wm_state()
8920 				hw_wm_level->lines);  in verify_wm_state()
8923 		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;  in verify_wm_state()
8924 		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;  in verify_wm_state()
8928 			drm_err(&dev_priv->drm,  in verify_wm_state()
8930 				plane->base.base.id, plane->base.name,  in verify_wm_state()
8931 				sw_wm_level->enable,  in verify_wm_state()
8932 				sw_wm_level->blocks,  in verify_wm_state()
8933 				sw_wm_level->lines,  in verify_wm_state()
8934 				hw_wm_level->enable,  in verify_wm_state()
8935 				hw_wm_level->blocks,  in verify_wm_state()
8936 				hw_wm_level->lines);  in verify_wm_state()
8939 		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;  in verify_wm_state()
8940 		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;  in verify_wm_state()
8944 			drm_err(&dev_priv->drm,  in verify_wm_state()
8946 				plane->base.base.id, plane->base.name,  in verify_wm_state()
8947 				sw_wm_level->enable,  in verify_wm_state()
8948 				sw_wm_level->blocks,  in verify_wm_state()
8949 				sw_wm_level->lines,  in verify_wm_state()
8950 				hw_wm_level->enable,  in verify_wm_state()
8951 				hw_wm_level->blocks,  in verify_wm_state()
8952 				hw_wm_level->lines);  in verify_wm_state()
8956 		hw_ddb_entry = &hw->ddb_y[plane->id];  in verify_wm_state()
8957 		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];  in verify_wm_state()
8960 			drm_err(&dev_priv->drm,  in verify_wm_state()
8962 				plane->base.base.id, plane->base.name,  in verify_wm_state()
8963 				sw_ddb_entry->start, sw_ddb_entry->end,  in verify_wm_state()
8964 				hw_ddb_entry->start, hw_ddb_entry->end);  in verify_wm_state()
8979 	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {  in verify_connector_state()
8980 		struct drm_encoder *encoder = connector->encoder;  in verify_connector_state()
8983 		if (new_conn_state->crtc != &crtc->base)  in verify_connector_state()
8991 		I915_STATE_WARN(new_conn_state->best_encoder != encoder,  in verify_connector_state()
9004 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in verify_encoder_state()
9008 		drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",  in verify_encoder_state()
9009 			    encoder->base.base.id,  in verify_encoder_state()
9010 			    encoder->base.name);  in verify_encoder_state()
9012 		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,  in verify_encoder_state()
9014 			if (old_conn_state->best_encoder == &encoder->base)  in verify_encoder_state()
9017 			if (new_conn_state->best_encoder != &encoder->base)  in verify_encoder_state()
9021 			I915_STATE_WARN(new_conn_state->crtc !=  in verify_encoder_state()
9022 					encoder->base.crtc,  in verify_encoder_state()
9029 		I915_STATE_WARN(!!encoder->base.crtc != enabled,  in verify_encoder_state()
9032 		     !!encoder->base.crtc, enabled);  in verify_encoder_state()
9034 		if (!encoder->base.crtc) {  in verify_encoder_state()
9037 			active = encoder->get_hw_state(encoder, &pipe);  in verify_encoder_state()
9050 	struct drm_device *dev = crtc->base.dev;  in verify_crtc_state()
9054 	struct drm_atomic_state *state = old_crtc_state->uapi.state;  in verify_crtc_state()
9057 	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);  in verify_crtc_state()
9060 	old_crtc_state->uapi.state = state;  in verify_crtc_state()
9062 	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,  in verify_crtc_state()
9063 		    crtc->base.name);  in verify_crtc_state()
9065 	pipe_config->hw.enable = new_crtc_state->hw.enable;  in verify_crtc_state()
9070 	if (IS_I830(dev_priv) && pipe_config->hw.active)  in verify_crtc_state()
9071 		pipe_config->hw.active = new_crtc_state->hw.active;  in verify_crtc_state()
9073 	I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,  in verify_crtc_state()
9076 			new_crtc_state->hw.active, pipe_config->hw.active);  in verify_crtc_state()
9078 	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,  in verify_crtc_state()
9081 			new_crtc_state->hw.active, crtc->active);  in verify_crtc_state()
9083 	if (new_crtc_state->bigjoiner_slave)  in verify_crtc_state()
9084 		master = new_crtc_state->bigjoiner_linked_crtc;  in verify_crtc_state()
9086 	for_each_encoder_on_crtc(dev, &master->base, encoder) {  in verify_crtc_state()
9090 		active = encoder->get_hw_state(encoder, &pipe);  in verify_crtc_state()
9091 		I915_STATE_WARN(active != new_crtc_state->hw.active,  in verify_crtc_state()
9093 				encoder->base.base.id, active,  in verify_crtc_state()
9094 				new_crtc_state->hw.active);  in verify_crtc_state()
9096 		I915_STATE_WARN(active && master->pipe != pipe,  in verify_crtc_state()
9104 	if (!new_crtc_state->hw.active)  in verify_crtc_state()
9107 	if (new_crtc_state->bigjoiner_slave)  in verify_crtc_state()
9109 		pipe_config->shared_dpll = NULL;  in verify_crtc_state()
9130 		assert_plane(plane, plane_state->planar_slave ||  in intel_verify_planes()
9131 			     plane_state->uapi.visible);  in intel_verify_planes()
9146 	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);  in verify_single_dpll_state()
9150 	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {  in verify_single_dpll_state()
9151 		I915_STATE_WARN(!pll->on && pll->active_mask,  in verify_single_dpll_state()
9153 		I915_STATE_WARN(pll->on && !pll->active_mask,  in verify_single_dpll_state()
9155 		I915_STATE_WARN(pll->on != active,  in verify_single_dpll_state()
9157 		     pll->on, active);  in verify_single_dpll_state()
9161 		I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,  in verify_single_dpll_state()
9163 				pll->active_mask, pll->state.pipe_mask);  in verify_single_dpll_state()
9168 	pipe_mask = BIT(crtc->pipe);  in verify_single_dpll_state()
9170 	if (new_crtc_state->hw.active)  in verify_single_dpll_state()
9171 		I915_STATE_WARN(!(pll->active_mask & pipe_mask),  in verify_single_dpll_state()
9173 				pipe_name(crtc->pipe), pll->active_mask);  in verify_single_dpll_state()
9175 		I915_STATE_WARN(pll->active_mask & pipe_mask,  in verify_single_dpll_state()
9177 				pipe_name(crtc->pipe), pll->active_mask);  in verify_single_dpll_state()
9179 	I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),  in verify_single_dpll_state()
9181 			pipe_mask, pll->state.pipe_mask);  in verify_single_dpll_state()
9183 	I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,  in verify_single_dpll_state()
9194 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in verify_shared_dpll_state()
9196 	if (new_crtc_state->shared_dpll)  in verify_shared_dpll_state()
9197 		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);  in verify_shared_dpll_state()
9199 	if (old_crtc_state->shared_dpll &&  in verify_shared_dpll_state()
9200 	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {  in verify_shared_dpll_state()
9201 		u8 pipe_mask = BIT(crtc->pipe);  in verify_shared_dpll_state()
9202 		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;  in verify_shared_dpll_state()
9204 		I915_STATE_WARN(pll->active_mask & pipe_mask,  in verify_shared_dpll_state()
9206 				pipe_name(crtc->pipe), pll->active_mask);  in verify_shared_dpll_state()
9207 		I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,  in verify_shared_dpll_state()
9209 				pipe_name(crtc->pipe), pll->state.pipe_mask);  in verify_shared_dpll_state()
9217 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in verify_mpllb_state()
9219 	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;  in verify_mpllb_state()
9220 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in verify_mpllb_state()
9226 	if (!new_crtc_state->hw.active)  in verify_mpllb_state()
9229 	if (new_crtc_state->bigjoiner_slave)  in verify_mpllb_state()
9236 	if (mpllb_sw_state->name != mpllb_hw_state.name) { \  in verify_mpllb_state()
9239 				     mpllb_sw_state->name, \  in verify_mpllb_state()
9268 	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)  in intel_modeset_verify_crtc()
9283 	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)  in verify_disabled_dpll_state()
9285 					 &dev_priv->dpll.shared_dplls[i],  in verify_disabled_dpll_state()
9300 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_all_pipes()
9307 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_all_pipes()
9311 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes()
9315 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes()
9316 		    drm_atomic_crtc_needs_modeset(&crtc_state->uapi))  in intel_modeset_all_pipes()
9319 		crtc_state->uapi.mode_changed = true;  in intel_modeset_all_pipes()
9321 		ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_all_pipes()
9322 							 &crtc->base);  in intel_modeset_all_pipes()
9330 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes()
9339 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_update_active_timings()
9340 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_update_active_timings()
9342 		crtc_state->hw.adjusted_mode;  in intel_crtc_update_active_timings()
9344 	if (crtc_state->vrr.enable) {  in intel_crtc_update_active_timings()
9345 		adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;  in intel_crtc_update_active_timings()
9346 		adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;  in intel_crtc_update_active_timings()
9348 		crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);  in intel_crtc_update_active_timings()
9351 	drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);  in intel_crtc_update_active_timings()
9353 	crtc->mode_flags = crtc_state->mode_flags;  in intel_crtc_update_active_timings()
9358 	 * On most platforms it starts counting from vtotal-1 on the  in intel_crtc_update_active_timings()
9362 	 * last active line), the scanline counter will read vblank_start-1.  in intel_crtc_update_active_timings()
9365 	 * of vtotal-1, so we have to subtract one (or rather add vtotal-1  in intel_crtc_update_active_timings()
9389 		crtc->scanline_offset = vtotal - 1;  in intel_crtc_update_active_timings()
9392 		crtc->scanline_offset = 2;  in intel_crtc_update_active_timings()
9394 		crtc->scanline_offset = 1;  in intel_crtc_update_active_timings()
9400 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_clear_plls()
9405 	if (!dev_priv->display.crtc_compute_clock)  in intel_modeset_clear_plls()
9433 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
9442 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
9451 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
9452 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
9456 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
9458 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
9466 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
9470 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
9472 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
9485 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
9486 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
9488 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
9496 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_checks()
9498 	state->modeset = true;  in intel_modeset_checks()
9508  * phase.  The code here should be run after the per-crtc and per-plane 'check'
9513 	struct drm_device *dev = state->base.dev;  in calc_watermark_data()
9516 	/* Is there platform-specific watermark information to calculate? */  in calc_watermark_data()
9517 	if (dev_priv->display.compute_global_watermarks)  in calc_watermark_data()
9518 		return dev_priv->display.compute_global_watermarks(state);  in calc_watermark_data()
9529 	new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
9530 	new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
9544 	new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;  in intel_crtc_copy_fastset()
9545 	new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;  in intel_crtc_copy_fastset()
9546 	new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;  in intel_crtc_copy_fastset()
9547 	new_crtc_state->has_drrs = old_crtc_state->has_drrs;  in intel_crtc_copy_fastset()
9554 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_crtc_add_planes_to_state()
9557 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_crtc_add_planes_to_state()
9560 		if ((plane_ids_mask & BIT(plane->id)) == 0)  in intel_crtc_add_planes_to_state()
9580 					      old_crtc_state->enabled_planes |  in intel_atomic_add_affected_planes()
9581 					      new_crtc_state->enabled_planes);  in intel_atomic_add_affected_planes()
9602 		if (plane->pipe == crtc->pipe)  in intel_crtc_add_bigjoiner_planes()
9603 			plane_ids |= BIT(plane->id);  in intel_crtc_add_bigjoiner_planes()
9618 		if (!crtc_state->bigjoiner)  in intel_bigjoiner_add_affected_planes()
9622 						      crtc_state->bigjoiner_linked_crtc);  in intel_bigjoiner_add_affected_planes()
9632 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_check_planes()
9650 			drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_check_planes()
9652 				       plane->base.base.id, plane->base.name);  in intel_atomic_check_planes()
9673 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
9674 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
9690 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_check_cdclk()
9715 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)  in intel_atomic_check_cdclk()
9718 	ret = dev_priv->display.bw_calc_min_cdclk(state);  in intel_atomic_check_cdclk()
9728 		min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);  in intel_atomic_check_cdclk()
9733 		if (new_bw_state->min_cdclk > min_cdclk)  in intel_atomic_check_cdclk()
9747 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_atomic_check_crtcs()
9752 			drm_dbg_atomic(&i915->drm,  in intel_atomic_check_crtcs()
9754 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
9770 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
9771 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
9788 	if (old_crtc_state->bigjoiner_slave) {  in intel_atomic_check_bigjoiner()
9790 		master = old_crtc_state->bigjoiner_linked_crtc;  in intel_atomic_check_bigjoiner()
9796 	if (!new_crtc_state->bigjoiner)  in intel_atomic_check_bigjoiner()
9803 			      crtc->base.base.id, crtc->base.name);  in intel_atomic_check_bigjoiner()
9804 		return -EINVAL;  in intel_atomic_check_bigjoiner()
9807 	new_crtc_state->bigjoiner_linked_crtc = slave;  in intel_atomic_check_bigjoiner()
9808 	slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);  in intel_atomic_check_bigjoiner()
9814 	if (slave_crtc_state->uapi.enable)  in intel_atomic_check_bigjoiner()
9818 		      slave->base.base.id, slave->base.name);  in intel_atomic_check_bigjoiner()
9825 		      slave->base.base.id, slave->base.name,  in intel_atomic_check_bigjoiner()
9826 		      master->base.base.id, master->base.name);  in intel_atomic_check_bigjoiner()
9827 	return -EINVAL;  in intel_atomic_check_bigjoiner()
9834 		intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);  in kill_bigjoiner_slave()
9836 	slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;  in kill_bigjoiner_slave()
9837 	slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;  in kill_bigjoiner_slave()
9838 	slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;  in kill_bigjoiner_slave()
9862 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_async()
9872 			drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");  in intel_atomic_check_async()
9873 			return -EINVAL;  in intel_atomic_check_async()
9876 		if (!new_crtc_state->hw.active) {  in intel_atomic_check_async()
9877 			drm_dbg_kms(&i915->drm, "CRTC inactive\n");  in intel_atomic_check_async()
9878 			return -EINVAL;  in intel_atomic_check_async()
9880 		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_atomic_check_async()
9881 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9883 			return -EINVAL;  in intel_atomic_check_async()
9896 		if (!plane->async_flip)  in intel_atomic_check_async()
9897 			return -EINVAL;  in intel_atomic_check_async()
9904 		switch (new_plane_state->hw.fb->modifier) {  in intel_atomic_check_async()
9910 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9911 				    "Linear memory/CCS does not support async flips\n");  in intel_atomic_check_async()
9912 			return -EINVAL;  in intel_atomic_check_async()
9915 		if (old_plane_state->view.color_plane[0].stride !=  in intel_atomic_check_async()
9916 		    new_plane_state->view.color_plane[0].stride) {  in intel_atomic_check_async()
9917 			drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");  in intel_atomic_check_async()
9918 			return -EINVAL;  in intel_atomic_check_async()
9921 		if (old_plane_state->hw.fb->modifier !=  in intel_atomic_check_async()
9922 		    new_plane_state->hw.fb->modifier) {  in intel_atomic_check_async()
9923 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9925 			return -EINVAL;  in intel_atomic_check_async()
9928 		if (old_plane_state->hw.fb->format !=  in intel_atomic_check_async()
9929 		    new_plane_state->hw.fb->format) {  in intel_atomic_check_async()
9930 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9932 			return -EINVAL;  in intel_atomic_check_async()
9935 		if (old_plane_state->hw.rotation !=  in intel_atomic_check_async()
9936 		    new_plane_state->hw.rotation) {  in intel_atomic_check_async()
9937 			drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");  in intel_atomic_check_async()
9938 			return -EINVAL;  in intel_atomic_check_async()
9941 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_atomic_check_async()
9942 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_atomic_check_async()
9943 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9944 				    "Plane size/co-ordinates cannot be changed in async flip\n");  in intel_atomic_check_async()
9945 			return -EINVAL;  in intel_atomic_check_async()
9948 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_atomic_check_async()
9949 			drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");  in intel_atomic_check_async()
9950 			return -EINVAL;  in intel_atomic_check_async()
9953 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_atomic_check_async()
9954 		    new_plane_state->hw.pixel_blend_mode) {  in intel_atomic_check_async()
9955 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9957 			return -EINVAL;  in intel_atomic_check_async()
9960 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_atomic_check_async()
9961 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_async()
9963 			return -EINVAL;  in intel_atomic_check_async()
9966 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_atomic_check_async()
9967 			drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");  in intel_atomic_check_async()
9968 			return -EINVAL;  in intel_atomic_check_async()
9986 		if (!crtc_state->bigjoiner)  in intel_bigjoiner_add_affected_crtcs()
9989 		linked_crtc = crtc_state->bigjoiner_linked_crtc;  in intel_bigjoiner_add_affected_crtcs()
9990 		linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);  in intel_bigjoiner_add_affected_crtcs()
9997 		linked_crtc_state->uapi.mode_changed = true;  in intel_bigjoiner_add_affected_crtcs()
9999 		ret = drm_atomic_add_affected_connectors(&state->base,  in intel_bigjoiner_add_affected_crtcs()
10000 							 &linked_crtc->base);  in intel_bigjoiner_add_affected_crtcs()
10010 		/* Kill old bigjoiner link, we may re-establish afterwards */  in intel_bigjoiner_add_affected_crtcs()
10012 		    crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)  in intel_bigjoiner_add_affected_crtcs()
10020  * intel_atomic_check - validate state object
10036 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
10037 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
10042 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
10059 		if (!new_crtc_state->uapi.enable) {  in intel_atomic_check()
10060 			if (!new_crtc_state->bigjoiner_slave) {  in intel_atomic_check()
10105 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
10109 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
10112 				new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
10113 				new_crtc_state->update_pipe = false;  in intel_atomic_check()
10118 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
10120 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
10121 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
10124 				new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
10125 				new_crtc_state->update_pipe = false;  in intel_atomic_check()
10129 		if (new_crtc_state->bigjoiner) {  in intel_atomic_check()
10131 				intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);  in intel_atomic_check()
10134 				new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
10135 				new_crtc_state->update_pipe = false;  in intel_atomic_check()
10147 		if (!new_crtc_state->update_pipe)  in intel_atomic_check()
10154 		drm_dbg_kms(&dev_priv->drm,  in intel_atomic_check()
10156 		ret = -EINVAL;  in intel_atomic_check()
10160 	ret = drm_dp_mst_atomic_check(&state->base);  in intel_atomic_check()
10202 		if (new_crtc_state->uapi.async_flip) {  in intel_atomic_check()
10209 		    !new_crtc_state->update_pipe)  in intel_atomic_check()
10220 	if (ret == -EDEADLK)  in intel_atomic_check()
10240 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
10247 		if (mode_changed || crtc_state->update_pipe ||  in intel_atomic_prepare_commit()
10248 		    crtc_state->uapi.color_mgmt_changed) {  in intel_atomic_prepare_commit()
10259 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_arm_fifo_underrun()
10261 	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
10262 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
10264 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
10275 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
10276 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pipe_fastset()
10290 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
10293 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
10295 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
10318 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_pre_planes()
10330 		if (new_crtc_state->uapi.color_mgmt_changed ||  in commit_pipe_pre_planes()
10331 		    new_crtc_state->update_pipe)  in commit_pipe_pre_planes()
10337 		if (new_crtc_state->update_pipe)  in commit_pipe_pre_planes()
10343 	if (dev_priv->display.atomic_update_watermarks)  in commit_pipe_pre_planes()
10344 		dev_priv->display.atomic_update_watermarks(state, crtc);  in commit_pipe_pre_planes()
10350 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_post_planes()
10367 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_enable_crtc()
10376 	dev_priv->display.crtc_enable(state, crtc);  in intel_enable_crtc()
10378 	if (new_crtc_state->bigjoiner_slave)  in intel_enable_crtc()
10381 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
10388 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_update_crtc()
10396 		if (new_crtc_state->preload_luts &&  in intel_update_crtc()
10397 		    (new_crtc_state->uapi.color_mgmt_changed ||  in intel_update_crtc()
10398 		     new_crtc_state->update_pipe))  in intel_update_crtc()
10403 		if (new_crtc_state->update_pipe)  in intel_update_crtc()
10407 	if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)  in intel_update_crtc()
10432 	if (new_crtc_state->update_pipe && !modeset &&  in intel_update_crtc()
10433 	    old_crtc_state->inherited)  in intel_update_crtc()
10442 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_old_crtc_state_disables()
10444 	drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);  in intel_old_crtc_state_disables()
10455 	if (old_crtc_state->bigjoiner) {  in intel_old_crtc_state_disables()
10457 					  old_crtc_state->bigjoiner_linked_crtc);  in intel_old_crtc_state_disables()
10458 		old_crtc_state->bigjoiner_linked_crtc->active = false;  in intel_old_crtc_state_disables()
10467 	dev_priv->display.crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
10468 	crtc->active = false;  in intel_old_crtc_state_disables()
10473 	if (!new_crtc_state->hw.active &&  in intel_old_crtc_state_disables()
10475 	    dev_priv->display.initial_watermarks)  in intel_old_crtc_state_disables()
10476 		dev_priv->display.initial_watermarks(state, crtc);  in intel_old_crtc_state_disables()
10489 		if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)  in intel_commit_modeset_disables()
10492 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
10507 		handled |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
10514 		    (handled & BIT(crtc->pipe)) ||  in intel_commit_modeset_disables()
10515 		    old_crtc_state->bigjoiner_slave)  in intel_commit_modeset_disables()
10519 		if (old_crtc_state->bigjoiner) {  in intel_commit_modeset_disables()
10521 				old_crtc_state->bigjoiner_linked_crtc;  in intel_commit_modeset_disables()
10526 		if (old_crtc_state->hw.active)  in intel_commit_modeset_disables()
10539 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
10549 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in skl_commit_modeset_enables()
10557 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
10559 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
10564 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
10583 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
10588 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
10592 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
10603 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
10604 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
10617 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
10624 		    (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))  in skl_commit_modeset_enables()
10637 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
10651 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
10656 		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
10659 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
10665 	drm_WARN_ON(&dev_priv->drm, modeset_pipes);  in skl_commit_modeset_enables()
10666 	drm_WARN_ON(&dev_priv->drm, update_pipes);  in skl_commit_modeset_enables()
10674 	freed = llist_del_all(&dev_priv->atomic_helper.free_list);  in intel_atomic_helper_free_state()
10676 		drm_atomic_state_put(&state->base);  in intel_atomic_helper_free_state()
10690 	struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
10695 		prepare_to_wait(&intel_state->commit_ready.wait,  in intel_atomic_commit_fence_wait()
10697 		prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,  in intel_atomic_commit_fence_wait()
10702 		if (i915_sw_fence_done(&intel_state->commit_ready) ||  in intel_atomic_commit_fence_wait()
10703 		    test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))  in intel_atomic_commit_fence_wait()
10708 	finish_wait(&intel_state->commit_ready.wait, &wait_fence);  in intel_atomic_commit_fence_wait()
10709 	finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,  in intel_atomic_commit_fence_wait()
10729 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_cleanup_work()
10732 	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);  in intel_atomic_cleanup_work()
10733 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
10734 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
10741 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_prepare_plane_clear_colors()
10747 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
10751 		    fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)  in intel_atomic_prepare_plane_clear_colors()
10757 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
10759 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
10761 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
10768 						     fb->offsets[2] + 16,  in intel_atomic_prepare_plane_clear_colors()
10769 						     &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
10770 						     sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
10772 		drm_WARN_ON(&i915->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
10778 	struct drm_device *dev = state->base.dev;  in intel_atomic_commit_tail()
10788 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
10790 	if (state->modeset)  in intel_atomic_commit_tail()
10798 		    new_crtc_state->update_pipe) {  in intel_atomic_commit_tail()
10800 			put_domains[crtc->pipe] =  in intel_atomic_commit_tail()
10807 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
10809 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
10811 	if (state->modeset) {  in intel_atomic_commit_tail()
10812 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);  in intel_atomic_commit_tail()
10826 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
10827 			spin_lock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
10828 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
10829 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
10830 			spin_unlock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
10832 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
10836 	if (state->modeset)  in intel_atomic_commit_tail()
10842 		if (new_crtc_state->uapi.async_flip)  in intel_atomic_commit_tail()
10847 	dev_priv->display.commit_modeset_enables(state);  in intel_atomic_commit_tail()
10849 	if (state->modeset) {  in intel_atomic_commit_tail()
10858 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
10859 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
10860 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
10861 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
10864 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);  in intel_atomic_commit_tail()
10867 		if (new_crtc_state->uapi.async_flip)  in intel_atomic_commit_tail()
10870 		if (new_crtc_state->hw.active &&  in intel_atomic_commit_tail()
10872 		    !new_crtc_state->preload_luts &&  in intel_atomic_commit_tail()
10873 		    (new_crtc_state->uapi.color_mgmt_changed ||  in intel_atomic_commit_tail()
10874 		     new_crtc_state->update_pipe))  in intel_atomic_commit_tail()
10880 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
10889 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
10896 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_atomic_commit_tail()
10898 		if (dev_priv->display.optimize_watermarks)  in intel_atomic_commit_tail()
10899 			dev_priv->display.optimize_watermarks(state, crtc);  in intel_atomic_commit_tail()
10907 		modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
10916 		old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);  in intel_atomic_commit_tail()
10923 	if (state->modeset)  in intel_atomic_commit_tail()
10928 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
10930 	if (state->modeset) {  in intel_atomic_commit_tail()
10934 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
10937 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
10940 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit_tail()
10945 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
10950 	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
10951 	queue_work(system_highpri_wq, &state->base.commit_work);  in intel_atomic_commit_tail()
10976 				&to_i915(state->base.dev)->atomic_helper;  in intel_atomic_commit_ready()
10978 			if (llist_add(&state->freed, &helper->free_list))  in intel_atomic_commit_ready()
10979 				schedule_work(&helper->free_work);  in intel_atomic_commit_ready()
10995 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
10996 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
10997 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
11008 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_atomic_commit()
11010 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
11011 	i915_sw_fence_init(&state->commit_ready,  in intel_atomic_commit()
11022 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
11031 	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
11037 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
11038 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
11039 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
11044 		drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_commit()
11046 		i915_sw_fence_commit(&state->commit_ready);  in intel_atomic_commit()
11047 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
11051 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_commit()
11053 		ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_commit()
11062 		i915_sw_fence_commit(&state->commit_ready);  in intel_atomic_commit()
11067 		drm_atomic_helper_cleanup_planes(dev, &state->base);  in intel_atomic_commit()
11068 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
11074 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
11075 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
11077 	i915_sw_fence_commit(&state->commit_ready);  in intel_atomic_commit()
11078 	if (nonblock && state->modeset) {  in intel_atomic_commit()
11079 		queue_work(dev_priv->modeset_wq, &state->base.commit_work);  in intel_atomic_commit()
11081 		queue_work(dev_priv->flip_wq, &state->base.commit_work);  in intel_atomic_commit()
11083 		if (state->modeset)  in intel_atomic_commit()
11084 			flush_workqueue(dev_priv->modeset_wq);  in intel_atomic_commit()
11102 	struct i915_request *rq = wait->request;  in do_rps_boost()
11113 	drm_crtc_vblank_put(wait->crtc);  in do_rps_boost()
11115 	list_del(&wait->wait.entry);  in do_rps_boost()
11128 	if (DISPLAY_VER(to_i915(crtc->dev)) < 6)  in add_rps_boost_after_vblank()
11140 	wait->request = to_request(dma_fence_get(fence));  in add_rps_boost_after_vblank()
11141 	wait->crtc = crtc;  in add_rps_boost_after_vblank()
11143 	wait->wait.func = do_rps_boost;  in add_rps_boost_after_vblank()
11144 	wait->wait.flags = 0;  in add_rps_boost_after_vblank()
11146 	add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);  in add_rps_boost_after_vblank()
11151 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_pin_fb()
11152 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_plane_pin_fb()
11153 	struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_plane_pin_fb()
11156 		plane->id == PLANE_CURSOR &&  in intel_plane_pin_fb()
11157 		INTEL_INFO(dev_priv)->display.cursor_needs_physical;  in intel_plane_pin_fb()
11161 						 &plane_state->view.gtt,  in intel_plane_pin_fb()
11163 						 &plane_state->flags);  in intel_plane_pin_fb()
11167 		plane_state->ggtt_vma = vma;  in intel_plane_pin_fb()
11171 		vma = intel_dpt_pin(intel_fb->dpt_vm);  in intel_plane_pin_fb()
11175 		plane_state->ggtt_vma = vma;  in intel_plane_pin_fb()
11177 		vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,  in intel_plane_pin_fb()
11178 					   &plane_state->flags, intel_fb->dpt_vm);  in intel_plane_pin_fb()
11180 			intel_dpt_unpin(intel_fb->dpt_vm);  in intel_plane_pin_fb()
11181 			plane_state->ggtt_vma = NULL;  in intel_plane_pin_fb()
11185 		plane_state->dpt_vma = vma;  in intel_plane_pin_fb()
11187 		WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);  in intel_plane_pin_fb()
11195 	struct drm_framebuffer *fb = old_plane_state->hw.fb;  in intel_plane_unpin_fb()
11199 		vma = fetch_and_zero(&old_plane_state->ggtt_vma);  in intel_plane_unpin_fb()
11201 			intel_unpin_fb_vma(vma, old_plane_state->flags);  in intel_plane_unpin_fb()
11205 		vma = fetch_and_zero(&old_plane_state->dpt_vma);  in intel_plane_unpin_fb()
11207 			intel_unpin_fb_vma(vma, old_plane_state->flags);  in intel_plane_unpin_fb()
11209 		vma = fetch_and_zero(&old_plane_state->ggtt_vma);  in intel_plane_unpin_fb()
11211 			intel_dpt_unpin(intel_fb->dpt_vm);  in intel_plane_unpin_fb()
11216  * intel_prepare_plane_fb - Prepare fb for usage on plane
11236 		to_intel_atomic_state(new_plane_state->uapi.state);  in intel_prepare_plane_fb()
11237 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_prepare_plane_fb()
11240 	struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);  in intel_prepare_plane_fb()
11241 	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);  in intel_prepare_plane_fb()
11247 							to_intel_crtc(old_plane_state->hw.crtc));  in intel_prepare_plane_fb()
11261 			ret = i915_sw_fence_await_reservation(&state->commit_ready,  in intel_prepare_plane_fb()
11262 							      old_obj->base.resv, NULL,  in intel_prepare_plane_fb()
11270 	if (new_plane_state->uapi.fence) { /* explicit fencing */  in intel_prepare_plane_fb()
11271 		i915_gem_fence_wait_priority(new_plane_state->uapi.fence,  in intel_prepare_plane_fb()
11273 		ret = i915_sw_fence_await_dma_fence(&state->commit_ready,  in intel_prepare_plane_fb()
11274 						    new_plane_state->uapi.fence,  in intel_prepare_plane_fb()
11292 	if (!new_plane_state->uapi.fence) { /* implicit fencing */  in intel_prepare_plane_fb()
11295 		ret = i915_sw_fence_await_reservation(&state->commit_ready,  in intel_prepare_plane_fb()
11296 						      obj->base.resv, NULL,  in intel_prepare_plane_fb()
11303 		fence = dma_resv_get_excl_unlocked(obj->base.resv);  in intel_prepare_plane_fb()
11305 			add_rps_boost_after_vblank(new_plane_state->hw.crtc,  in intel_prepare_plane_fb()
11310 		add_rps_boost_after_vblank(new_plane_state->hw.crtc,  in intel_prepare_plane_fb()
11311 					   new_plane_state->uapi.fence);  in intel_prepare_plane_fb()
11322 	if (!state->rps_interactive) {  in intel_prepare_plane_fb()
11323 		intel_rps_mark_interactive(&dev_priv->gt.rps, true);  in intel_prepare_plane_fb()
11324 		state->rps_interactive = true;  in intel_prepare_plane_fb()
11336  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11349 		to_intel_atomic_state(old_plane_state->uapi.state);  in intel_cleanup_plane_fb()
11350 	struct drm_i915_private *dev_priv = to_i915(plane->dev);  in intel_cleanup_plane_fb()
11351 	struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);  in intel_cleanup_plane_fb()
11356 	if (state->rps_interactive) {  in intel_cleanup_plane_fb()
11357 		intel_rps_mark_interactive(&dev_priv->gt.rps, false);  in intel_cleanup_plane_fb()
11358 		state->rps_interactive = false;  in intel_cleanup_plane_fb()
11366  * intel_plane_destroy - destroy a plane
11382 	for_each_intel_plane(&dev_priv->drm, plane) {  in intel_plane_possible_crtcs_init()
11384 								  plane->pipe);  in intel_plane_possible_crtcs_init()
11386 		plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);  in intel_plane_possible_crtcs_init()
11398 	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);  in intel_get_pipe_from_crtc_id_ioctl()
11400 		return -ENOENT;  in intel_get_pipe_from_crtc_id_ioctl()
11403 	pipe_from_crtc_id->pipe = crtc->pipe;  in intel_get_pipe_from_crtc_id_ioctl()
11410 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_clones()
11416 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
11424 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_crtcs()
11429 		if (encoder->pipe_mask & BIT(crtc->pipe))  in intel_encoder_possible_crtcs()
11430 			possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
11466 	if (!dev_priv->vbt.int_crt_support)  in intel_ddi_crt_present()
11599 		if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)  in intel_setup_outputs()
11605 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
11612 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
11656 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");  in intel_setup_outputs()
11659 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
11671 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");  in intel_setup_outputs()
11678 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
11699 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_setup_outputs()
11700 		encoder->base.possible_crtcs =  in intel_setup_outputs()
11702 		encoder->base.possible_clones =  in intel_setup_outputs()
11708 	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);  in intel_setup_outputs()
11718 		intel_dpt_destroy(intel_fb->dpt_vm);  in intel_user_framebuffer_destroy()
11720 	intel_frontbuffer_put(intel_fb->frontbuffer);  in intel_user_framebuffer_destroy()
11730 	struct drm_i915_private *i915 = to_i915(obj->base.dev);  in intel_user_framebuffer_create_handle()
11733 		drm_dbg(&i915->drm,  in intel_user_framebuffer_create_handle()
11735 		return -EINVAL;  in intel_user_framebuffer_create_handle()
11738 	return drm_gem_handle_create(file, &obj->base, handle);  in intel_user_framebuffer_create_handle()
11765 	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);  in intel_framebuffer_init()
11766 	struct drm_framebuffer *fb = &intel_fb->base;  in intel_framebuffer_init()
11769 	int ret = -EINVAL;  in intel_framebuffer_init()
11772 	intel_fb->frontbuffer = intel_frontbuffer_get(obj);  in intel_framebuffer_init()
11773 	if (!intel_fb->frontbuffer)  in intel_framebuffer_init()
11774 		return -ENOMEM;  in intel_framebuffer_init()
11781 	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {  in intel_framebuffer_init()
11787 		    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {  in intel_framebuffer_init()
11788 			drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11794 			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;  in intel_framebuffer_init()
11796 			drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11802 	if (!drm_any_plane_has_format(&dev_priv->drm,  in intel_framebuffer_init()
11803 				      mode_cmd->pixel_format,  in intel_framebuffer_init()
11804 				      mode_cmd->modifier[0])) {  in intel_framebuffer_init()
11805 		drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11807 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);  in intel_framebuffer_init()
11816 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {  in intel_framebuffer_init()
11817 		drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11822 	max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,  in intel_framebuffer_init()
11823 					 mode_cmd->modifier[0]);  in intel_framebuffer_init()
11824 	if (mode_cmd->pitches[0] > max_stride) {  in intel_framebuffer_init()
11825 		drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11827 			    mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?  in intel_framebuffer_init()
11829 			    mode_cmd->pitches[0], max_stride);  in intel_framebuffer_init()
11837 	if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {  in intel_framebuffer_init()
11838 		drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11840 			    mode_cmd->pitches[0], stride);  in intel_framebuffer_init()
11845 	if (mode_cmd->offsets[0] != 0) {  in intel_framebuffer_init()
11846 		drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11848 			    mode_cmd->offsets[0]);  in intel_framebuffer_init()
11852 	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);  in intel_framebuffer_init()
11854 	for (i = 0; i < fb->format->num_planes; i++) {  in intel_framebuffer_init()
11857 		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {  in intel_framebuffer_init()
11858 			drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",  in intel_framebuffer_init()
11864 		if (fb->pitches[i] & (stride_alignment - 1)) {  in intel_framebuffer_init()
11865 			drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11867 				    i, fb->pitches[i], stride_alignment);  in intel_framebuffer_init()
11874 			if (fb->pitches[i] != ccs_aux_stride) {  in intel_framebuffer_init()
11875 				drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11876 					    "ccs aux plane %d pitch (%d) must be %d\n",  in intel_framebuffer_init()
11878 					    fb->pitches[i], ccs_aux_stride);  in intel_framebuffer_init()
11883 		/* TODO: Add POT stride remapping support for CCS formats as well. */  in intel_framebuffer_init()
11885 		    mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&  in intel_framebuffer_init()
11887 		    !is_power_of_2(mode_cmd->pitches[i])) {  in intel_framebuffer_init()
11888 			drm_dbg_kms(&dev_priv->drm,  in intel_framebuffer_init()
11890 				    i, mode_cmd->pitches[i]);  in intel_framebuffer_init()
11894 		fb->obj[i] = &obj->base;  in intel_framebuffer_init()
11910 		intel_fb->dpt_vm = vm;  in intel_framebuffer_init()
11913 	ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);  in intel_framebuffer_init()
11915 		drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);  in intel_framebuffer_init()
11922 	intel_frontbuffer_put(intel_fb->frontbuffer);  in intel_framebuffer_init()
11938 		return ERR_PTR(-ENOENT);  in intel_user_framebuffer_create()
11941 	i915 = to_i915(obj->base.dev);  in intel_user_framebuffer_create()
11945 		return ERR_PTR(-EREMOTE);  in intel_user_framebuffer_create()
11970 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
11971 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
11975 	if (mode->vscan > 1)  in intel_mode_valid()
11978 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
11981 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
11986 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
12015 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
12016 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
12017 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
12018 	    mode->htotal > htotal_max)  in intel_mode_valid()
12021 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
12022 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
12023 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
12024 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
12028 		if (mode->hdisplay < 64 ||  in intel_mode_valid()
12029 		    mode->htotal - mode->hdisplay < 32)  in intel_mode_valid()
12032 		if (mode->vtotal - mode->vdisplay < 5)  in intel_mode_valid()
12035 		if (mode->htotal - mode->hdisplay < 32)  in intel_mode_valid()
12038 		if (mode->vtotal - mode->vdisplay < 3)  in intel_mode_valid()
12072 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
12075 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
12094  * intel_init_display_hooks - initialize the display modesetting hooks
12108 		dev_priv->display.get_pipe_config = hsw_get_pipe_config;  in intel_init_display_hooks()
12109 		dev_priv->display.crtc_enable = hsw_crtc_enable;  in intel_init_display_hooks()
12110 		dev_priv->display.crtc_disable = hsw_crtc_disable;  in intel_init_display_hooks()
12112 		dev_priv->display.get_pipe_config = hsw_get_pipe_config;  in intel_init_display_hooks()
12113 		dev_priv->display.crtc_enable = hsw_crtc_enable;  in intel_init_display_hooks()
12114 		dev_priv->display.crtc_disable = hsw_crtc_disable;  in intel_init_display_hooks()
12116 		dev_priv->display.get_pipe_config = ilk_get_pipe_config;  in intel_init_display_hooks()
12117 		dev_priv->display.crtc_enable = ilk_crtc_enable;  in intel_init_display_hooks()
12118 		dev_priv->display.crtc_disable = ilk_crtc_disable;  in intel_init_display_hooks()
12121 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;  in intel_init_display_hooks()
12122 		dev_priv->display.crtc_enable = valleyview_crtc_enable;  in intel_init_display_hooks()
12123 		dev_priv->display.crtc_disable = i9xx_crtc_disable;  in intel_init_display_hooks()
12125 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;  in intel_init_display_hooks()
12126 		dev_priv->display.crtc_enable = i9xx_crtc_enable;  in intel_init_display_hooks()
12127 		dev_priv->display.crtc_disable = i9xx_crtc_disable;  in intel_init_display_hooks()
12133 		dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;  in intel_init_display_hooks()
12134 		dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;  in intel_init_display_hooks()
12136 		dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;  in intel_init_display_hooks()
12137 		dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;  in intel_init_display_hooks()
12149 	cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);  in intel_modeset_init_hw()
12152 	intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");  in intel_modeset_init_hw()
12153 	cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;  in intel_modeset_init_hw()
12161 	for_each_intel_crtc(state->dev, crtc) {  in sanitize_watermarks_add_affected()
12168 		if (crtc_state->hw.active) {  in sanitize_watermarks_add_affected()
12173 			crtc_state->inherited = true;  in sanitize_watermarks_add_affected()
12177 	drm_for_each_plane(plane, state->dev) {  in sanitize_watermarks_add_affected()
12209 	if (!dev_priv->display.optimize_watermarks)  in sanitize_watermarks()
12212 	state = drm_atomic_state_alloc(&dev_priv->drm);  in sanitize_watermarks()
12213 	if (drm_WARN_ON(&dev_priv->drm, !state))  in sanitize_watermarks()
12221 	state->acquire_ctx = &ctx;  in sanitize_watermarks()
12229 		intel_state->skip_intermediate_wm = true;  in sanitize_watermarks()
12235 	ret = intel_atomic_check(&dev_priv->drm, state);  in sanitize_watermarks()
12241 		crtc_state->wm.need_postvbl_update = true;  in sanitize_watermarks()
12242 		dev_priv->display.optimize_watermarks(intel_state, crtc);  in sanitize_watermarks()
12244 		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;  in sanitize_watermarks()
12248 	if (ret == -EDEADLK) {  in sanitize_watermarks()
12263 	 * BIOS-programmed watermarks untouched and hope for the best.  in sanitize_watermarks()
12265 	drm_WARN(&dev_priv->drm, ret,  in sanitize_watermarks()
12280 		dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;  in intel_update_fdi_pll_freq()
12282 		dev_priv->fdi_pll_freq = 270000;  in intel_update_fdi_pll_freq()
12287 	drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);  in intel_update_fdi_pll_freq()
12299 		return -ENOMEM;  in intel_initial_commit()
12304 	state->acquire_ctx = &ctx;  in intel_initial_commit()
12315 		if (crtc_state->hw.active) {  in intel_initial_commit()
12325 			crtc_state->inherited = true;  in intel_initial_commit()
12327 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
12337 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
12340 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
12341 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
12342 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
12344 										 &crtc->base);  in intel_initial_commit()
12355 	if (ret == -EDEADLK) {  in intel_initial_commit()
12371 	struct drm_mode_config *mode_config = &i915->drm.mode_config;  in intel_mode_config_init()
12373 	drm_mode_config_init(&i915->drm);  in intel_mode_config_init()
12374 	INIT_LIST_HEAD(&i915->global_obj_list);  in intel_mode_config_init()
12376 	mode_config->min_width = 0;  in intel_mode_config_init()
12377 	mode_config->min_height = 0;  in intel_mode_config_init()
12379 	mode_config->preferred_depth = 24;  in intel_mode_config_init()
12380 	mode_config->prefer_shadow = 1;  in intel_mode_config_init()
12382 	mode_config->funcs = &intel_mode_funcs;  in intel_mode_config_init()
12384 	mode_config->async_page_flip = has_async_flips(i915);  in intel_mode_config_init()
12391 		mode_config->max_width = 16384;  in intel_mode_config_init()
12392 		mode_config->max_height = 16384;  in intel_mode_config_init()
12394 		mode_config->max_width = 8192;  in intel_mode_config_init()
12395 		mode_config->max_height = 8192;  in intel_mode_config_init()
12397 		mode_config->max_width = 4096;  in intel_mode_config_init()
12398 		mode_config->max_height = 4096;  in intel_mode_config_init()
12400 		mode_config->max_width = 2048;  in intel_mode_config_init()
12401 		mode_config->max_height = 2048;  in intel_mode_config_init()
12405 		mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;  in intel_mode_config_init()
12406 		mode_config->cursor_height = 1023;  in intel_mode_config_init()
12409 		mode_config->cursor_width = 64;  in intel_mode_config_init()
12410 		mode_config->cursor_height = 64;  in intel_mode_config_init()
12412 		mode_config->cursor_width = 256;  in intel_mode_config_init()
12413 		mode_config->cursor_height = 256;  in intel_mode_config_init()
12420 	drm_mode_config_cleanup(&i915->drm);  in intel_mode_config_cleanup()
12425 	if (plane_config->fb) {  in plane_config_fini()
12426 		struct drm_framebuffer *fb = &plane_config->fb->base;  in plane_config_fini()
12435 	if (plane_config->vma)  in plane_config_fini()
12436 		i915_vma_put(plane_config->vma);  in plane_config_fini()
12445 		return -ENODEV;  in intel_modeset_init_noirq()
12448 		ret = drm_vblank_init(&i915->drm,  in intel_modeset_init_noirq()
12468 	i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);  in intel_modeset_init_noirq()
12469 	i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |  in intel_modeset_init_noirq()
12472 	i915->framestart_delay = 1; /* 1-4 */  in intel_modeset_init_noirq()
12474 	i915->window2_delay = 0; /* No DSB so no window2 delay */  in intel_modeset_init_noirq()
12490 	init_llist_head(&i915->atomic_helper.free_list);  in intel_modeset_init_noirq()
12491 	INIT_WORK(&i915->atomic_helper.free_work,  in intel_modeset_init_noirq()
12513 	struct drm_device *dev = &i915->drm;  in intel_modeset_init_nogem()
12529 	drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",  in intel_modeset_init_nogem()
12551 	if (i915->max_cdclk_freq == 0)  in intel_modeset_init_nogem()
12558 	if (INTEL_INFO(i915)->display.has_hti)  in intel_modeset_init_nogem()
12559 		i915->hti_state = intel_de_read(i915, HDPORT_STATE);  in intel_modeset_init_nogem()
12566 	intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);  in intel_modeset_init_nogem()
12572 		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)  in intel_modeset_init_nogem()
12582 		i915->display.get_initial_plane_config(crtc, &plane_config);  in intel_modeset_init_nogem()
12596 	 * since the watermark calculation done here will use pstate->fb.  in intel_modeset_init_nogem()
12618 	ret = intel_initial_commit(&i915->drm);  in intel_modeset_init()
12620 		drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);  in intel_modeset_init()
12624 	ret = intel_fbdev_init(&i915->drm);  in intel_modeset_init()
12651 	drm_WARN_ON(&dev_priv->drm,  in i830_enable_pipe()
12654 	drm_dbg_kms(&dev_priv->drm,  in i830_enable_pipe()
12661 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
12669 	intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));  in i830_enable_pipe()
12670 	intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));  in i830_enable_pipe()
12671 	intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));  in i830_enable_pipe()
12672 	intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));  in i830_enable_pipe()
12673 	intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));  in i830_enable_pipe()
12674 	intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));  in i830_enable_pipe()
12675 	intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));  in i830_enable_pipe()
12714 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
12717 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
12720 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
12723 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
12726 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
12728 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
12748 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_sanitize_plane_mapping()
12750 			to_intel_plane(crtc->base.primary);  in intel_sanitize_plane_mapping()
12754 		if (!plane->get_hw_state(plane, &pipe))  in intel_sanitize_plane_mapping()
12757 		if (pipe == crtc->pipe)  in intel_sanitize_plane_mapping()
12760 		drm_dbg_kms(&dev_priv->drm,  in intel_sanitize_plane_mapping()
12762 			    plane->base.base.id, plane->base.name);  in intel_sanitize_plane_mapping()
12771 	struct drm_device *dev = crtc->base.dev;  in intel_crtc_has_encoders()
12774 	for_each_encoder_on_crtc(dev, &crtc->base, encoder)  in intel_crtc_has_encoders()
12782 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_find_connector()
12785 	for_each_connector_on_encoder(dev, &encoder->base, connector)  in intel_encoder_find_connector()
12800 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_sanitize_frame_start_delay()
12801 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_sanitize_frame_start_delay()
12802 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_sanitize_frame_start_delay()
12814 		val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in intel_sanitize_frame_start_delay()
12822 		val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in intel_sanitize_frame_start_delay()
12826 	if (!crtc_state->has_pch_encoder)  in intel_sanitize_frame_start_delay()
12830 		i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);  in intel_sanitize_frame_start_delay()
12835 		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in intel_sanitize_frame_start_delay()
12844 		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);  in intel_sanitize_frame_start_delay()
12852 	struct drm_device *dev = crtc->base.dev;  in intel_sanitize_crtc()
12854 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_sanitize_crtc()
12856 	if (crtc_state->hw.active) {  in intel_sanitize_crtc()
12865 				to_intel_plane_state(plane->base.state);  in intel_sanitize_crtc()
12867 			if (plane_state->uapi.visible &&  in intel_sanitize_crtc()
12868 			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)  in intel_sanitize_crtc()
12877 			intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),  in intel_sanitize_crtc()
12883 	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&  in intel_sanitize_crtc()
12884 	    !crtc_state->bigjoiner_slave)  in intel_sanitize_crtc()
12887 	if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {  in intel_sanitize_crtc()
12898 		 * No protection against concurrent access is required - at  in intel_sanitize_crtc()
12901 		crtc->cpu_fifo_underrun_disabled = true;  in intel_sanitize_crtc()
12906 		 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,  in intel_sanitize_crtc()
12907 		 * and marking underrun reporting as disabled for the non-existing  in intel_sanitize_crtc()
12911 		if (has_pch_trancoder(dev_priv, crtc->pipe))  in intel_sanitize_crtc()
12912 			crtc->pch_fifo_underrun_disabled = true;  in intel_sanitize_crtc()
12918 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in has_bogus_dpll_config()
12931 		crtc_state->hw.active &&  in has_bogus_dpll_config()
12932 		crtc_state->shared_dpll &&  in has_bogus_dpll_config()
12933 		crtc_state->port_clock == 0;  in has_bogus_dpll_config()
12938 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_sanitize_encoder()
12940 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in intel_sanitize_encoder()
12942 		to_intel_crtc_state(crtc->base.state) : NULL;  in intel_sanitize_encoder()
12948 		crtc_state->hw.active;  in intel_sanitize_encoder()
12951 		drm_dbg_kms(&dev_priv->drm,  in intel_sanitize_encoder()
12953 			    pipe_name(crtc->pipe));  in intel_sanitize_encoder()
12959 		drm_dbg_kms(&dev_priv->drm,  in intel_sanitize_encoder()
12961 			    encoder->base.base.id,  in intel_sanitize_encoder()
12962 			    encoder->base.name);  in intel_sanitize_encoder()
12970 			drm_dbg_kms(&dev_priv->drm,  in intel_sanitize_encoder()
12972 				    encoder->base.base.id,  in intel_sanitize_encoder()
12973 				    encoder->base.name);  in intel_sanitize_encoder()
12976 			best_encoder = connector->base.state->best_encoder;  in intel_sanitize_encoder()
12977 			connector->base.state->best_encoder = &encoder->base;  in intel_sanitize_encoder()
12980 			if (encoder->disable)  in intel_sanitize_encoder()
12981 				encoder->disable(NULL, encoder, crtc_state,  in intel_sanitize_encoder()
12982 						 connector->base.state);  in intel_sanitize_encoder()
12983 			if (encoder->post_disable)  in intel_sanitize_encoder()
12984 				encoder->post_disable(NULL, encoder, crtc_state,  in intel_sanitize_encoder()
12985 						      connector->base.state);  in intel_sanitize_encoder()
12987 			connector->base.state->best_encoder = best_encoder;  in intel_sanitize_encoder()
12989 		encoder->base.crtc = NULL;  in intel_sanitize_encoder()
12996 		connector->base.dpms = DRM_MODE_DPMS_OFF;  in intel_sanitize_encoder()
12997 		connector->base.encoder = NULL;  in intel_sanitize_encoder()
13013 	for_each_intel_plane(&dev_priv->drm, plane) {  in readout_plane_state()
13015 			to_intel_plane_state(plane->base.state);  in readout_plane_state()
13020 		visible = plane->get_hw_state(plane, &pipe);  in readout_plane_state()
13023 		crtc_state = to_intel_crtc_state(crtc->base.state);  in readout_plane_state()
13027 		drm_dbg_kms(&dev_priv->drm,  in readout_plane_state()
13029 			    plane->base.base.id, plane->base.name,  in readout_plane_state()
13033 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in readout_plane_state()
13035 			to_intel_crtc_state(crtc->base.state);  in readout_plane_state()
13045 		to_intel_cdclk_state(dev_priv->cdclk.obj.state);  in intel_modeset_readout_hw_state()
13047 		to_intel_dbuf_state(dev_priv->dbuf.obj.state);  in intel_modeset_readout_hw_state()
13057 			to_intel_crtc_state(crtc->base.state);  in intel_modeset_readout_hw_state()
13059 		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);  in intel_modeset_readout_hw_state()
13065 		crtc_state->hw.enable = crtc_state->hw.active;  in intel_modeset_readout_hw_state()
13067 		crtc->base.enabled = crtc_state->hw.enable;  in intel_modeset_readout_hw_state()
13068 		crtc->active = crtc_state->hw.active;  in intel_modeset_readout_hw_state()
13070 		if (crtc_state->hw.active)  in intel_modeset_readout_hw_state()
13071 			active_pipes |= BIT(crtc->pipe);  in intel_modeset_readout_hw_state()
13073 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_readout_hw_state()
13075 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_readout_hw_state()
13076 			    enableddisabled(crtc_state->hw.active));  in intel_modeset_readout_hw_state()
13079 	dev_priv->active_pipes = cdclk_state->active_pipes =  in intel_modeset_readout_hw_state()
13080 		dbuf_state->active_pipes = active_pipes;  in intel_modeset_readout_hw_state()
13089 		if (encoder->get_hw_state(encoder, &pipe)) {  in intel_modeset_readout_hw_state()
13091 			crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_modeset_readout_hw_state()
13093 			encoder->base.crtc = &crtc->base;  in intel_modeset_readout_hw_state()
13097 			if (crtc_state->bigjoiner) {  in intel_modeset_readout_hw_state()
13099 				WARN_ON(crtc_state->bigjoiner_slave);  in intel_modeset_readout_hw_state()
13101 				crtc = crtc_state->bigjoiner_linked_crtc;  in intel_modeset_readout_hw_state()
13102 				crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_modeset_readout_hw_state()
13106 			encoder->base.crtc = NULL;  in intel_modeset_readout_hw_state()
13109 		if (encoder->sync_state)  in intel_modeset_readout_hw_state()
13110 			encoder->sync_state(encoder, crtc_state);  in intel_modeset_readout_hw_state()
13112 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_readout_hw_state()
13114 			    encoder->base.base.id, encoder->base.name,  in intel_modeset_readout_hw_state()
13115 			    enableddisabled(encoder->base.crtc),  in intel_modeset_readout_hw_state()
13123 		if (connector->get_hw_state(connector)) {  in intel_modeset_readout_hw_state()
13127 			connector->base.dpms = DRM_MODE_DPMS_ON;  in intel_modeset_readout_hw_state()
13130 			connector->base.encoder = &encoder->base;  in intel_modeset_readout_hw_state()
13132 			crtc = to_intel_crtc(encoder->base.crtc);  in intel_modeset_readout_hw_state()
13133 			crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;  in intel_modeset_readout_hw_state()
13135 			if (crtc_state && crtc_state->hw.active) {  in intel_modeset_readout_hw_state()
13141 				crtc_state->uapi.connector_mask |=  in intel_modeset_readout_hw_state()
13142 					drm_connector_mask(&connector->base);  in intel_modeset_readout_hw_state()
13143 				crtc_state->uapi.encoder_mask |=  in intel_modeset_readout_hw_state()
13144 					drm_encoder_mask(&encoder->base);  in intel_modeset_readout_hw_state()
13147 			connector->base.dpms = DRM_MODE_DPMS_OFF;  in intel_modeset_readout_hw_state()
13148 			connector->base.encoder = NULL;  in intel_modeset_readout_hw_state()
13150 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_readout_hw_state()
13152 			    connector->base.base.id, connector->base.name,  in intel_modeset_readout_hw_state()
13153 			    enableddisabled(connector->base.encoder));  in intel_modeset_readout_hw_state()
13159 			to_intel_bw_state(dev_priv->bw_obj.state);  in intel_modeset_readout_hw_state()
13161 			to_intel_crtc_state(crtc->base.state);  in intel_modeset_readout_hw_state()
13165 		if (crtc_state->bigjoiner_slave)  in intel_modeset_readout_hw_state()
13168 		if (crtc_state->hw.active) {  in intel_modeset_readout_hw_state()
13178 			crtc_state->inherited = true;  in intel_modeset_readout_hw_state()
13185 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_modeset_readout_hw_state()
13187 				to_intel_plane_state(plane->base.state);  in intel_modeset_readout_hw_state()
13193 			if (plane_state->uapi.visible)  in intel_modeset_readout_hw_state()
13194 				crtc_state->data_rate[plane->id] =  in intel_modeset_readout_hw_state()
13195 					4 * crtc_state->pixel_rate;  in intel_modeset_readout_hw_state()
13198 			 * use plane->min_cdclk() :(  in intel_modeset_readout_hw_state()
13200 			if (plane_state->uapi.visible && plane->min_cdclk) {  in intel_modeset_readout_hw_state()
13201 				if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)  in intel_modeset_readout_hw_state()
13202 					crtc_state->min_cdclk[plane->id] =  in intel_modeset_readout_hw_state()
13203 						DIV_ROUND_UP(crtc_state->pixel_rate, 2);  in intel_modeset_readout_hw_state()
13205 					crtc_state->min_cdclk[plane->id] =  in intel_modeset_readout_hw_state()
13206 						crtc_state->pixel_rate;  in intel_modeset_readout_hw_state()
13208 			drm_dbg_kms(&dev_priv->drm,  in intel_modeset_readout_hw_state()
13210 				    plane->base.base.id, plane->base.name,  in intel_modeset_readout_hw_state()
13211 				    crtc_state->min_cdclk[plane->id]);  in intel_modeset_readout_hw_state()
13214 		if (crtc_state->hw.active) {  in intel_modeset_readout_hw_state()
13220 		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;  in intel_modeset_readout_hw_state()
13221 		cdclk_state->min_voltage_level[crtc->pipe] =  in intel_modeset_readout_hw_state()
13222 			crtc_state->min_voltage_level;  in intel_modeset_readout_hw_state()
13229 		if (crtc_state->bigjoiner && crtc_state->hw.active) {  in intel_modeset_readout_hw_state()
13230 			struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;  in intel_modeset_readout_hw_state()
13232 				to_intel_crtc_state(slave->base.state);  in intel_modeset_readout_hw_state()
13235 			slave->base.mode = crtc->base.mode;  in intel_modeset_readout_hw_state()
13237 			cdclk_state->min_cdclk[slave->pipe] = min_cdclk;  in intel_modeset_readout_hw_state()
13238 			cdclk_state->min_voltage_level[slave->pipe] =  in intel_modeset_readout_hw_state()
13239 				crtc_state->min_voltage_level;  in intel_modeset_readout_hw_state()
13241 			for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {  in intel_modeset_readout_hw_state()
13243 					to_intel_plane_state(plane->base.state);  in intel_modeset_readout_hw_state()
13249 				if (plane_state->uapi.visible)  in intel_modeset_readout_hw_state()
13250 					crtc_state->data_rate[plane->id] =  in intel_modeset_readout_hw_state()
13251 						4 * crtc_state->pixel_rate;  in intel_modeset_readout_hw_state()
13253 					crtc_state->data_rate[plane->id] = 0;  in intel_modeset_readout_hw_state()
13257 			drm_calc_timestamping_constants(&slave->base,  in intel_modeset_readout_hw_state()
13258 							&slave_crtc_state->hw.adjusted_mode);  in intel_modeset_readout_hw_state()
13268 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in get_encoder_power_domains()
13271 		if (!encoder->get_power_domains)  in get_encoder_power_domains()
13275 		 * MST-primary and inactive encoders don't have a crtc state  in get_encoder_power_domains()
13278 		if (!encoder->base.crtc)  in get_encoder_power_domains()
13281 		crtc_state = to_intel_crtc_state(encoder->base.crtc->state);  in get_encoder_power_domains()
13282 		encoder->get_power_domains(encoder, crtc_state);  in get_encoder_power_domains()
13324 	drm_dbg_kms(&dev_priv->drm,  in ibx_sanitize_pch_hdmi_port()
13343 	drm_dbg_kms(&dev_priv->drm,  in ibx_sanitize_pch_dp_port()
13403 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_setup_hw_state()
13405 			to_intel_crtc_state(crtc->base.state);  in intel_modeset_setup_hw_state()
13407 		drm_crtc_vblank_reset(&crtc->base);  in intel_modeset_setup_hw_state()
13409 		if (crtc_state->hw.active)  in intel_modeset_setup_hw_state()
13418 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_setup_hw_state()
13420 			to_intel_crtc_state(crtc->base.state);  in intel_modeset_setup_hw_state()
13444 			to_intel_crtc_state(crtc->base.state);  in intel_modeset_setup_hw_state()
13458 	struct drm_atomic_state *state = dev_priv->modeset_restore_state;  in intel_display_resume()
13465 	dev_priv->modeset_restore_state = NULL;  in intel_display_resume()
13467 		state->acquire_ctx = &ctx;  in intel_display_resume()
13473 		if (ret != -EDEADLK)  in intel_display_resume()
13487 		drm_err(&dev_priv->drm,  in intel_display_resume()
13499 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_hpd_poll_fini()
13501 		if (connector->modeset_retry_work.func)  in intel_hpd_poll_fini()
13502 			cancel_work_sync(&connector->modeset_retry_work);  in intel_hpd_poll_fini()
13503 		if (connector->hdcp.shim) {  in intel_hpd_poll_fini()
13504 			cancel_delayed_work_sync(&connector->hdcp.check_work);  in intel_hpd_poll_fini()
13505 			cancel_work_sync(&connector->hdcp.prop_work);  in intel_hpd_poll_fini()
13517 	flush_workqueue(i915->flip_wq);  in intel_modeset_driver_remove()
13518 	flush_workqueue(i915->modeset_wq);  in intel_modeset_driver_remove()
13520 	flush_work(&i915->atomic_helper.free_work);  in intel_modeset_driver_remove()
13521 	drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));  in intel_modeset_driver_remove()
13531 	 * Due to the hpd irq storm handling the hotplug work can re-arm the  in intel_modeset_driver_remove_noirq()
13561 	destroy_workqueue(i915->flip_wq);  in intel_modeset_driver_remove_noirq()
13562 	destroy_workqueue(i915->modeset_wq);  in intel_modeset_driver_remove_noirq()
13593 	 * Some ports require correctly set-up hpd registers for  in intel_display_driver_register()
13600 	intel_fbdev_initial_config_async(&i915->drm);  in intel_display_driver_register()
13605 	 * fbdev->async_cookie.  in intel_display_driver_register()
13607 	drm_kms_helper_poll_init(&i915->drm);  in intel_display_driver_register()
13623 	drm_kms_helper_poll_fini(&i915->drm);  in intel_display_driver_unregister()
13624 	drm_atomic_helper_shutdown(&i915->drm);  in intel_display_driver_unregister()