Lines Matching +full:vco +full:- +full:offset
2 * Copyright © 2006-2017 Intel Corporation
65 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
71 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
77 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
83 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
89 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
95 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
101 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
109 if (pdev->revision == 0x1) { in i85x_get_cdclk()
110 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
114 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
124 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
127 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
130 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
135 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
143 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
149 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
155 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
159 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
167 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
173 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
179 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
183 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
228 unsigned int vco; in intel_hpll_vco() local
248 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
249 if (vco == 0) in intel_hpll_vco()
250 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
253 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
255 return vco; in intel_hpll_vco()
261 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
270 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
279 switch (cdclk_config->vco) { in g33_get_cdclk()
296 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
301 drm_err(&dev_priv->drm, in g33_get_cdclk()
302 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
303 cdclk_config->vco, tmp); in g33_get_cdclk()
304 cdclk_config->cdclk = 190476; in g33_get_cdclk()
310 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
317 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
320 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
323 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
326 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
329 drm_err(&dev_priv->drm, in pnv_get_cdclk()
333 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
336 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
344 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
352 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
356 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
361 switch (cdclk_config->vco) { in i965gm_get_cdclk()
375 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
380 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
381 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
382 cdclk_config->vco, tmp); in i965gm_get_cdclk()
383 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
389 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
393 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
399 switch (cdclk_config->vco) { in gm45_get_cdclk()
403 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
406 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
409 drm_err(&dev_priv->drm, in gm45_get_cdclk()
410 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
411 cdclk_config->vco, tmp); in gm45_get_cdclk()
412 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
424 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
426 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
428 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
430 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
432 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
437 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
470 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
482 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
483 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
485 cdclk_config->vco); in vlv_get_cdclk()
493 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
496 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
509 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
520 * WA - write default credits before re-programming in vlv_program_pfi_credits()
533 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
541 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
542 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
577 drm_err(&dev_priv->drm, in vlv_set_cdclk()
584 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
585 cdclk) - 1; in vlv_set_cdclk()
596 drm_err(&dev_priv->drm, in vlv_set_cdclk()
600 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
630 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
631 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
661 drm_err(&dev_priv->drm, in chv_set_cdclk()
708 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
710 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
712 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
714 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
716 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
718 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
724 cdclk_config->voltage_level = in bdw_get_cdclk()
725 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
749 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
752 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
764 drm_err(&dev_priv->drm, in bdw_set_cdclk()
778 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
788 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
791 cdclk_config->voltage_level); in bdw_set_cdclk()
794 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
799 static int skl_calc_cdclk(int min_cdclk, int vco) in skl_calc_cdclk() argument
801 if (vco == 8640000) { in skl_calc_cdclk()
839 cdclk_config->ref = 24000; in skl_dpll0_update()
840 cdclk_config->vco = 0; in skl_dpll0_update()
846 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
851 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
863 cdclk_config->vco = 8100000; in skl_dpll0_update()
867 cdclk_config->vco = 8640000; in skl_dpll0_update()
882 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
884 if (cdclk_config->vco == 0) in skl_get_cdclk()
889 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
892 cdclk_config->cdclk = 432000; in skl_get_cdclk()
895 cdclk_config->cdclk = 308571; in skl_get_cdclk()
898 cdclk_config->cdclk = 540000; in skl_get_cdclk()
901 cdclk_config->cdclk = 617143; in skl_get_cdclk()
910 cdclk_config->cdclk = 450000; in skl_get_cdclk()
913 cdclk_config->cdclk = 337500; in skl_get_cdclk()
916 cdclk_config->cdclk = 540000; in skl_get_cdclk()
919 cdclk_config->cdclk = 675000; in skl_get_cdclk()
932 cdclk_config->voltage_level = in skl_get_cdclk()
933 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
936 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
939 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
943 int vco) in skl_set_preferred_cdclk_vco() argument
945 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
947 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
953 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
955 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
959 * taking into account the VCO required to operate the eDP panel at the in skl_dpll0_link_rate()
960 * desired frequency. The usual DP link rates operate with a VCO of in skl_dpll0_link_rate()
961 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. in skl_dpll0_link_rate()
964 * works with vco. in skl_dpll0_link_rate()
966 if (vco == 8640000) in skl_dpll0_link_rate()
972 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
979 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
986 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
988 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
990 /* We'll want to keep using the current vco from now on. */ in skl_dpll0_enable()
991 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1000 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1002 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
1006 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1010 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1011 cdclk != dev_priv->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1012 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1032 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1033 int vco = cdclk_config->vco; in skl_set_cdclk() local
1042 * use the corresponding VCO freq as that always leads to using the in skl_set_cdclk()
1045 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1046 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1053 drm_err(&dev_priv->drm, in skl_set_cdclk()
1058 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1060 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1061 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1066 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1078 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1079 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1095 cdclk_config->voltage_level); in skl_set_cdclk()
1105 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1107 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1113 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1116 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1117 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1123 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1128 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1134 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1137 dev_priv->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1139 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1148 if (dev_priv->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1149 dev_priv->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1151 * Use the current vco as our initial in skl_cdclk_init_hw()
1152 * guess as to what the preferred vco is. in skl_cdclk_init_hw()
1154 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1156 dev_priv->cdclk.hw.vco); in skl_cdclk_init_hw()
1160 cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_init_hw()
1162 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1163 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1164 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1165 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1173 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_uninit_hw()
1176 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1294 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk()
1298 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk()
1302 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1304 min_cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk()
1310 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk_pll_vco()
1313 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1317 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1319 return dev_priv->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1321 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1322 cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1375 cdclk_config->ref = 24000; in icl_readout_refclk()
1378 cdclk_config->ref = 19200; in icl_readout_refclk()
1381 cdclk_config->ref = 38400; in icl_readout_refclk()
1392 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1396 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1402 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1405 cdclk_config->vco = 0; in bxt_de_pll_readout()
1418 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1430 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1432 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1434 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1436 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1437 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1461 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1468 cdclk_config->voltage_level = in bxt_get_cdclk()
1469 dev_priv->display.calc_voltage_level(cdclk_config->cdclk); in bxt_get_cdclk()
1479 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1481 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1484 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1486 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1496 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1498 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1508 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1510 dev_priv->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1513 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1515 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in icl_cdclk_pll_enable()
1526 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1528 dev_priv->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1531 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1533 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1552 dev_priv->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1576 int cdclk, int vco) in bxt_cdclk_cd2x_div_sel() argument
1578 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1579 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_cdclk_cd2x_div_sel()
1581 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1582 cdclk != dev_priv->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1583 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1600 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1601 int vco = cdclk_config->vco; in bxt_set_cdclk() local
1621 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1627 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { in bxt_set_cdclk()
1628 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1629 adlp_cdclk_pll_crawl(dev_priv, vco); in bxt_set_cdclk()
1631 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1632 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1635 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1636 icl_cdclk_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1638 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1639 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1642 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1643 bxt_de_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1646 val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) | in bxt_set_cdclk()
1664 cdclk_config->voltage_level); in bxt_set_cdclk()
1674 cdclk_config->voltage_level, in bxt_set_cdclk()
1679 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1692 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1698 int cdclk, vco; in bxt_sanitize_cdclk() local
1701 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1703 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1704 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1722 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1723 if (cdclk != dev_priv->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1726 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
1727 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1728 if (vco != dev_priv->cdclk.hw.vco) in bxt_sanitize_cdclk()
1735 dev_priv->cdclk.hw.cdclk, in bxt_sanitize_cdclk()
1736 dev_priv->cdclk.hw.vco); in bxt_sanitize_cdclk()
1743 dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1751 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1754 dev_priv->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1757 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1766 if (dev_priv->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1767 dev_priv->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1770 cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_init_hw()
1774 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
1778 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1780 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_init_hw()
1787 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_uninit_hw()
1790 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
1792 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
1798 * intel_cdclk_init_hw - Initialize CDCLK hardware
1801 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1815 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1839 * The vco and cd2x divider will change independently in intel_cdclk_can_crawl()
1842 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
1843 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
1845 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
1846 a->vco != b->vco && in intel_cdclk_can_crawl()
1848 a->ref == b->ref; in intel_cdclk_can_crawl()
1852 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1864 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
1865 a->vco != b->vco || in intel_cdclk_needs_modeset()
1866 a->ref != b->ref; in intel_cdclk_needs_modeset()
1870 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1888 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
1889 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
1890 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
1894 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1905 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
1911 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_dump_cdclk_config()
1912 context, cdclk_config->cdclk, cdclk_config->vco, in intel_dump_cdclk_config()
1913 cdclk_config->ref, cdclk_config->bypass, in intel_dump_cdclk_config()
1914 cdclk_config->voltage_level); in intel_dump_cdclk_config()
1918 * intel_set_cdclk - Push the CDCLK configuration to the hardware
1932 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) in intel_set_cdclk()
1935 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) in intel_set_cdclk()
1940 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
1951 mutex_lock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1952 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1955 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
1956 &dev_priv->gmbus_mutex); in intel_set_cdclk()
1959 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
1961 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1964 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
1966 mutex_unlock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1968 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
1974 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
1975 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), in intel_set_cdclk()
1977 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); in intel_set_cdclk()
1983 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1992 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
1997 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
1999 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2000 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2004 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2005 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2007 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
2012 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2021 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
2026 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2028 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2029 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2033 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { in intel_set_cdclk_post_plane_update()
2034 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2036 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2042 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
2043 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2052 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
2060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
2065 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2066 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2074 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2077 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2092 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2093 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2094 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2108 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2119 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2120 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2157 min_t(int, crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2158 dev_priv->max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2161 if (min_cdclk > dev_priv->max_cdclk_freq) { in intel_crtc_compute_min_cdclk()
2162 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_min_cdclk()
2164 min_cdclk, dev_priv->max_cdclk_freq); in intel_crtc_compute_min_cdclk()
2165 return -EINVAL; in intel_crtc_compute_min_cdclk()
2173 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2174 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2192 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2195 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2197 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2202 min_cdclk = cdclk_state->force_min_cdclk; in intel_compute_min_cdclk()
2204 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2209 min_cdclk = max(bw_state->min_cdclk, min_cdclk); in intel_compute_min_cdclk()
2230 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2231 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2241 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2242 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2246 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2249 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2251 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2258 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2266 struct intel_atomic_state *state = cdclk_state->base.state; in vlv_modeset_calc_cdclk()
2267 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2276 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2277 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2280 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2281 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2283 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2284 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2287 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2307 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2308 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2311 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2312 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2314 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2315 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2318 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
2326 struct intel_atomic_state *state = cdclk_state->base.state; in skl_dpll0_vco()
2327 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
2330 int vco, i; in skl_dpll0_vco() local
2332 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2333 if (!vco) in skl_dpll0_vco()
2334 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2337 if (!crtc_state->hw.enable) in skl_dpll0_vco()
2344 * DPLL0 VCO may need to be adjusted to get the correct in skl_dpll0_vco()
2347 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
2350 vco = 8640000; in skl_dpll0_vco()
2353 vco = 8100000; in skl_dpll0_vco()
2358 return vco; in skl_dpll0_vco()
2363 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2369 vco = skl_dpll0_vco(cdclk_state); in skl_modeset_calc_cdclk()
2375 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2377 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2378 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2379 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
2382 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
2383 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2385 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2386 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2387 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
2390 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
2398 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_modeset_calc_cdclk()
2399 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
2400 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
2411 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2413 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2414 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2415 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
2417 dev_priv->display.calc_voltage_level(cdclk)); in bxt_modeset_calc_cdclk()
2419 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
2420 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2421 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2423 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
2424 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2425 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
2426 dev_priv->display.calc_voltage_level(cdclk); in bxt_modeset_calc_cdclk()
2428 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
2454 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
2458 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
2460 return &cdclk_state->base; in intel_cdclk_duplicate_state()
2477 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
2480 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); in intel_atomic_get_cdclk_state()
2493 return -ENOMEM; in intel_cdclk_init()
2495 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, in intel_cdclk_init()
2496 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
2503 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
2515 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
2516 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2518 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); in intel_modeset_calc_cdclk()
2522 if (intel_cdclk_changed(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2523 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2528 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2531 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
2532 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
2533 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
2534 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
2535 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2542 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
2544 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2545 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2549 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2552 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
2556 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) in intel_modeset_calc_cdclk()
2561 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2562 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2563 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2566 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
2568 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2571 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2572 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2578 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2582 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2584 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
2585 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
2586 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2588 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
2589 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
2596 int max_cdclk_freq = dev_priv->max_cdclk_freq; in intel_compute_max_dotclk()
2612 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2622 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2623 dev_priv->max_cdclk_freq = 552000; in intel_update_max_cdclk()
2625 dev_priv->max_cdclk_freq = 556800; in intel_update_max_cdclk()
2627 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2628 dev_priv->max_cdclk_freq = 648000; in intel_update_max_cdclk()
2630 dev_priv->max_cdclk_freq = 652800; in intel_update_max_cdclk()
2632 dev_priv->max_cdclk_freq = 316800; in intel_update_max_cdclk()
2634 dev_priv->max_cdclk_freq = 624000; in intel_update_max_cdclk()
2637 int max_cdclk, vco; in intel_update_max_cdclk() local
2639 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2640 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
2643 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
2645 * if the preferred vco is 8100 instead. in intel_update_max_cdclk()
2656 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2665 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2667 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2669 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
2671 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
2673 dev_priv->max_cdclk_freq = 320000; in intel_update_max_cdclk()
2675 dev_priv->max_cdclk_freq = 400000; in intel_update_max_cdclk()
2678 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2681 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
2683 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
2684 dev_priv->max_cdclk_freq); in intel_update_max_cdclk()
2686 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
2687 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
2691 * intel_update_cdclk - Determine the current CDCLK frequency
2698 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2708 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
2743 fraction) - 1); in cnp_rawclk()
2821 * intel_read_rawclk - Determine the current RAWCLK frequency
2849 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2855 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2856 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2857 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2858 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2859 dev_priv->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
2861 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2862 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2863 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2864 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2865 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
2867 dev_priv->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
2869 dev_priv->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
2871 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2872 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2873 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2874 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2875 dev_priv->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
2877 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2878 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2879 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2880 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2881 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2883 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2884 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2885 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2886 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; in intel_init_cdclk_hooks()
2887 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2889 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2890 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2891 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2892 dev_priv->display.calc_voltage_level = icl_calc_voltage_level; in intel_init_cdclk_hooks()
2893 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2895 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2896 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2897 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2898 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; in intel_init_cdclk_hooks()
2900 dev_priv->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
2902 dev_priv->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
2904 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2905 dev_priv->display.set_cdclk = skl_set_cdclk; in intel_init_cdclk_hooks()
2906 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2908 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2909 dev_priv->display.set_cdclk = bdw_set_cdclk; in intel_init_cdclk_hooks()
2910 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2912 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2913 dev_priv->display.set_cdclk = chv_set_cdclk; in intel_init_cdclk_hooks()
2914 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2916 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2917 dev_priv->display.set_cdclk = vlv_set_cdclk; in intel_init_cdclk_hooks()
2918 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2920 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2921 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2925 dev_priv->display.get_cdclk = bxt_get_cdclk; in intel_init_cdclk_hooks()
2927 dev_priv->display.get_cdclk = skl_get_cdclk; in intel_init_cdclk_hooks()
2929 dev_priv->display.get_cdclk = bdw_get_cdclk; in intel_init_cdclk_hooks()
2931 dev_priv->display.get_cdclk = hsw_get_cdclk; in intel_init_cdclk_hooks()
2933 dev_priv->display.get_cdclk = vlv_get_cdclk; in intel_init_cdclk_hooks()
2935 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2937 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; in intel_init_cdclk_hooks()
2939 dev_priv->display.get_cdclk = gm45_get_cdclk; in intel_init_cdclk_hooks()
2941 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2943 dev_priv->display.get_cdclk = i965gm_get_cdclk; in intel_init_cdclk_hooks()
2945 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2947 dev_priv->display.get_cdclk = pnv_get_cdclk; in intel_init_cdclk_hooks()
2949 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2951 dev_priv->display.get_cdclk = i945gm_get_cdclk; in intel_init_cdclk_hooks()
2953 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2955 dev_priv->display.get_cdclk = i915gm_get_cdclk; in intel_init_cdclk_hooks()
2957 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; in intel_init_cdclk_hooks()
2959 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; in intel_init_cdclk_hooks()
2961 dev_priv->display.get_cdclk = i85x_get_cdclk; in intel_init_cdclk_hooks()
2963 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; in intel_init_cdclk_hooks()
2965 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()
2967 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk, in intel_init_cdclk_hooks()
2969 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()