Lines Matching full:ratio
1183 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1184 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1185 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1186 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1192 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1193 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1194 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1199 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1200 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1201 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1202 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1203 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1204 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1206 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1207 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1208 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1209 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1210 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1211 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1213 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1214 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1215 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1216 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1217 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1218 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1223 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1224 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1225 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1226 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1227 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1228 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1230 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1231 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1232 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1233 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1234 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1235 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1237 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1238 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1239 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1240 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1241 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1242 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1247 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1248 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1249 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1251 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1252 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1253 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1255 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1256 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1257 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1262 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1263 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1264 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1265 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1266 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1268 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1269 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1270 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1271 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1272 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1274 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1275 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1276 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1277 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1278 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1283 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1284 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1285 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1286 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1287 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1288 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1319 return dev_priv->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1389 u32 val, ratio; in bxt_de_pll_readout() local
1402 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1410 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, in bxt_de_pll_readout()
1414 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; in bxt_de_pll_readout()
1416 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1418 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1486 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable() local
1489 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); in bxt_de_pll_enable()
1515 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in icl_cdclk_pll_enable() local
1518 val = ICL_CDCLK_PLL_RATIO(ratio); in icl_cdclk_pll_enable()
1533 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in adlp_cdclk_pll_crawl() local
1536 /* Write PLL ratio without disabling */ in adlp_cdclk_pll_crawl()
1537 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; in adlp_cdclk_pll_crawl()
2302 * FIXME should also account for plane ratio in bdw_modeset_calc_cdclk()
2372 * FIXME should also account for plane ratio in skl_modeset_calc_cdclk()