Lines Matching full:vco
228 unsigned int vco; in intel_hpll_vco() local
248 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
249 if (vco == 0) in intel_hpll_vco()
250 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
253 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
255 return vco; in intel_hpll_vco()
270 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
279 switch (cdclk_config->vco) { in g33_get_cdclk()
296 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
302 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
303 cdclk_config->vco, tmp); in g33_get_cdclk()
352 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
361 switch (cdclk_config->vco) { in i965gm_get_cdclk()
375 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
381 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
382 cdclk_config->vco, tmp); in i965gm_get_cdclk()
393 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
399 switch (cdclk_config->vco) { in gm45_get_cdclk()
410 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
411 cdclk_config->vco, tmp); in gm45_get_cdclk()
482 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
485 cdclk_config->vco); in vlv_get_cdclk()
799 static int skl_calc_cdclk(int min_cdclk, int vco) in skl_calc_cdclk() argument
801 if (vco == 8640000) { in skl_calc_cdclk()
840 cdclk_config->vco = 0; in skl_dpll0_update()
863 cdclk_config->vco = 8100000; in skl_dpll0_update()
867 cdclk_config->vco = 8640000; in skl_dpll0_update()
884 if (cdclk_config->vco == 0) in skl_get_cdclk()
889 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
943 int vco) in skl_set_preferred_cdclk_vco() argument
945 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
947 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
953 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
955 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
959 * taking into account the VCO required to operate the eDP panel at the in skl_dpll0_link_rate()
960 * desired frequency. The usual DP link rates operate with a VCO of in skl_dpll0_link_rate()
961 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. in skl_dpll0_link_rate()
964 * works with vco. in skl_dpll0_link_rate()
966 if (vco == 8640000) in skl_dpll0_link_rate()
972 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
979 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
988 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
990 /* We'll want to keep using the current vco from now on. */ in skl_dpll0_enable()
991 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1002 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
1006 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1012 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1033 int vco = cdclk_config->vco; in skl_set_cdclk() local
1042 * use the corresponding VCO freq as that always leads to using the in skl_set_cdclk()
1046 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1058 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1060 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1061 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1066 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1078 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1079 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1116 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1139 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1149 dev_priv->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1151 * Use the current vco as our initial in skl_cdclk_init_hw()
1152 * guess as to what the preferred vco is. in skl_cdclk_init_hw()
1156 dev_priv->cdclk.hw.vco); in skl_cdclk_init_hw()
1162 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1163 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1164 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1165 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1176 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1402 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1405 cdclk_config->vco = 0; in bxt_de_pll_readout()
1418 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1436 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1461 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1481 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1484 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1486 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1498 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1510 dev_priv->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1513 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1515 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in icl_cdclk_pll_enable()
1528 dev_priv->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1531 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1533 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1552 dev_priv->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1576 int cdclk, int vco) in bxt_cdclk_cd2x_div_sel() argument
1578 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1579 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_cdclk_cd2x_div_sel()
1583 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1601 int vco = cdclk_config->vco; in bxt_set_cdclk() local
1627 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { in bxt_set_cdclk()
1628 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1629 adlp_cdclk_pll_crawl(dev_priv, vco); in bxt_set_cdclk()
1631 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1632 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1635 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1636 icl_cdclk_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1638 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1639 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1642 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1643 bxt_de_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1646 val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) | in bxt_set_cdclk()
1698 int cdclk, vco; in bxt_sanitize_cdclk() local
1703 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1726 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
1727 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1728 if (vco != dev_priv->cdclk.hw.vco) in bxt_sanitize_cdclk()
1736 dev_priv->cdclk.hw.vco); in bxt_sanitize_cdclk()
1757 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1767 dev_priv->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1778 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1790 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
1839 * The vco and cd2x divider will change independently in intel_cdclk_can_crawl()
1842 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
1843 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
1845 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
1846 a->vco != b->vco && in intel_cdclk_can_crawl()
1865 a->vco != b->vco || in intel_cdclk_needs_modeset()
1889 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
1911 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_dump_cdclk_config()
1912 context, cdclk_config->cdclk, cdclk_config->vco, in intel_dump_cdclk_config()
2330 int vco, i; in skl_dpll0_vco() local
2332 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2333 if (!vco) in skl_dpll0_vco()
2334 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2344 * DPLL0 VCO may need to be adjusted to get the correct in skl_dpll0_vco()
2350 vco = 8640000; in skl_dpll0_vco()
2353 vco = 8100000; in skl_dpll0_vco()
2358 return vco; in skl_dpll0_vco()
2363 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2369 vco = skl_dpll0_vco(cdclk_state); in skl_modeset_calc_cdclk()
2375 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2377 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2383 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2385 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2400 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
2411 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2413 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2421 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2423 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
2637 int max_cdclk, vco; in intel_update_max_cdclk() local
2639 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2640 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
2643 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
2645 * if the preferred vco is 8100 instead. in intel_update_max_cdclk()
2656 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()