Lines Matching refs:dpll
583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
659 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
670 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
716 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
752 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
761 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
762 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
767 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
836 u32 dpll; in cdv_intel_crtc_clock_get() local
843 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
844 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
851 dpll = p->dpll; in cdv_intel_crtc_clock_get()
852 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
867 ffs((dpll & in cdv_intel_crtc_clock_get()
872 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
876 if ((dpll & PLL_REF_INPUT_MASK) == in cdv_intel_crtc_clock_get()
883 if (dpll & PLL_P1_DIVIDE_BY_TWO) in cdv_intel_crtc_clock_get()
887 ((dpll & in cdv_intel_crtc_clock_get()
891 if (dpll & PLL_P2_DIVIDE_BY_4) in cdv_intel_crtc_clock_get()