27 #define CDV_LIMIT_SINGLE_LVDS_96	0
40 	 .m1 = {.min = 0, .max = 0},
52 	 .m1 = {.min = 0, .max = 0},
67 	 .m1 = {.min = 0, .max = 0},
79 	 .m1 = {.min = 0, .max = 0},
91 	 .m1 = {.min = 0, .max = 0},
103 	 .m1 = {.min = 0, .max = 0},
114 	int ret__ = 0;							\
133 	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);  in cdv_sb_read()
143 		   SET_FIELD(0xf, SB_BYTE_ENABLE));  in cdv_sb_read()
145 	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);  in cdv_sb_read()
153 	return 0;  in cdv_sb_read()
163 		if (cdv_sb_read(dev, reg, &temp) == 0)  in cdv_sb_write()
164 			DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);  in cdv_sb_write()
165 		DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);  in cdv_sb_write()
168 	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);  in cdv_sb_write()
179 		   SET_FIELD(0xf, SB_BYTE_ENABLE));  in cdv_sb_write()
181 	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);  in cdv_sb_write()
188 		if (cdv_sb_read(dev, reg, &temp) == 0)  in cdv_sb_write()
189 			DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);  in cdv_sb_write()
192 	return 0;  in cdv_sb_write()
201 	REG_WRITE(DPIO_CFG, 0);  in cdv_sb_reset()
218 	int ret = 0;  in cdv_dpll_set_clock_cdv()
219 	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;  in cdv_dpll_set_clock_cdv()
220 	int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;  in cdv_dpll_set_clock_cdv()
231 	ref_value = 0x68A701;  in cdv_dpll_set_clock_cdv()
239 	 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk  in cdv_dpll_set_clock_cdv()
281 	n_vco &= 0xFFFF;  in cdv_dpll_set_clock_cdv()
282 	n_vco |= 0x107;  in cdv_dpll_set_clock_cdv()
291 		n_vco |= (0 << SB_N_VCO_SEL_SHIFT);  in cdv_dpll_set_clock_cdv()
296 		n_vco |= (0 << SB_N_CB_TUNE_SHIFT);  in cdv_dpll_set_clock_cdv()
299 		n_vco |= (0 << SB_N_CB_TUNE_SHIFT);  in cdv_dpll_set_clock_cdv()
360 	return 0;  in cdv_dpll_set_clock_cdv()
391 /* m1 is reserved as 0 in CDV, n is a ring counter */
408 	memset(&clock, 0, sizeof(clock));  in cdv_intel_find_dp_pll()
416 			clock.m1 = 0;  in cdv_intel_find_dp_pll()
422 			clock.m1 = 0;  in cdv_intel_find_dp_pll()
432 			clock.m1 = 0;  in cdv_intel_find_dp_pll()
438 			clock.m1 = 0;  in cdv_intel_find_dp_pll()
452 #define		FIFO_PIPEA		(1 << 0)
482 		REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);  in cdv_disable_sr()
496 	if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {  in cdv_update_wm()
501 		fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);  in cdv_update_wm()
503 		fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);  in cdv_update_wm()
508 		fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);  in cdv_update_wm()
510 		fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);  in cdv_update_wm()
513 		REG_WRITE(DSPFW3, 0x36000000);  in cdv_update_wm()
520 			REG_WRITE(DSPFW5, 0x00040330);  in cdv_update_wm()
529 		REG_WRITE(DSPFW6, 0x10);  in cdv_update_wm()
541 		REG_WRITE(DSPFW1, 0x3f880808);  in cdv_update_wm()
542 		REG_WRITE(DSPFW2, 0x0b020202);  in cdv_update_wm()
543 		REG_WRITE(DSPFW3, 0x24000000);  in cdv_update_wm()
544 		REG_WRITE(DSPFW4, 0x08030202);  in cdv_update_wm()
545 		REG_WRITE(DSPFW5, 0x01010101);  in cdv_update_wm()
546 		REG_WRITE(DSPFW6, 0x1d0);  in cdv_update_wm()
565 	if ((pfit_control & PFIT_ENABLE) == 0)  in cdv_intel_panel_fitter_pipe()
567 	return (pfit_control >> 29) & 0x3;  in cdv_intel_panel_fitter_pipe()
583 	u32 dpll = 0, dspcntr, pipeconf;  in cdv_intel_crtc_mode_set()
590 	u32 ddi_select = 0;  in cdv_intel_crtc_mode_set()
617 			return 0;  in cdv_intel_crtc_mode_set()
636 		if (pipe == 0)  in cdv_intel_crtc_mode_set()
656 		return 0;  in cdv_intel_crtc_mode_set()
664 		REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);  in cdv_intel_crtc_mode_set()
665 		REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);  in cdv_intel_crtc_mode_set()
666 		REG_WRITE(PIPE_DP_LINK_M(pipe), 0);  in cdv_intel_crtc_mode_set()
667 		REG_WRITE(PIPE_DP_LINK_N(pipe), 0);  in cdv_intel_crtc_mode_set()
708 	if (pipe == 0)  in cdv_intel_crtc_mode_set()
756 		REG_WRITE(PFIT_CONTROL, 0);  in cdv_intel_crtc_mode_set()
758 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');  in cdv_intel_crtc_mode_set()
774 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U…  in cdv_intel_crtc_mode_set()
794 	REG_WRITE(map->pos, 0);  in cdv_intel_crtc_mode_set()
813 	return 0;  in cdv_intel_crtc_mode_set()
844 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
852 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
870 		if (clock.p1 == 0) {  in cdv_intel_crtc_clock_get()
940 	mode->hdisplay = (htot & 0xffff) + 1;  in cdv_intel_crtc_mode_get()
941 	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;  in cdv_intel_crtc_mode_get()
942 	mode->hsync_start = (hsync & 0xffff) + 1;  in cdv_intel_crtc_mode_get()
943 	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;  in cdv_intel_crtc_mode_get()
944 	mode->vdisplay = (vtot & 0xffff) + 1;  in cdv_intel_crtc_mode_get()
945 	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;  in cdv_intel_crtc_mode_get()
946 	mode->vsync_start = (vsync & 0xffff) + 1;  in cdv_intel_crtc_mode_get()
947 	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;  in cdv_intel_crtc_mode_get()
950 	drm_mode_set_crtcinfo(mode, 0);  in cdv_intel_crtc_mode_get()