477 			       const u8 port_cap[4], u8 type)  in drm_dp_downstream_is_type()
481 		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;  in drm_dp_downstream_is_type()
494 			       const u8 port_cap[4],  in drm_dp_downstream_is_tmds()
506 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_is_tmds()
723 				   const u8 port_cap[4])  in drm_dp_downstream_max_dotclock()
731 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_dotclock()
735 		return port_cap[1] * 8000;  in drm_dp_downstream_max_dotclock()
752 				     const u8 port_cap[4],  in drm_dp_downstream_max_tmds_clock()
767 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_tmds_clock()
795 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
800 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
817 				     const u8 port_cap[4],  in drm_dp_downstream_min_tmds_clock()
832 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_min_tmds_clock()
860 			      const u8 port_cap[4],  in drm_dp_downstream_max_bpc()
875 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_bpc()
888 		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {  in drm_dp_downstream_max_bpc()
916 				       const u8 port_cap[4])  in drm_dp_downstream_420_passthrough()
924 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_420_passthrough()
931 		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;  in drm_dp_downstream_420_passthrough()
947 					     const u8 port_cap[4])  in drm_dp_downstream_444_to_420_conversion()
955 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_444_to_420_conversion()
960 		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;  in drm_dp_downstream_444_to_420_conversion()
978 					       const u8 port_cap[4],  in drm_dp_downstream_rgb_to_ycbcr_conversion()
987 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_rgb_to_ycbcr_conversion()
992 		return port_cap[3] & color_spc;  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1012 		       const u8 port_cap[4])  in drm_dp_downstream_mode()
1023 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_mode()
1025 		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {  in drm_dp_downstream_mode()
1078 			     const u8 port_cap[4],  in drm_dp_downstream_debug()
1089 	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_downstream_debug()
1138 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);  in drm_dp_downstream_debug()
1142 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1146 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1150 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1165 			 const u8 port_cap[4])  in drm_dp_subconnector_type()
1189 	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_subconnector_type()
1222 				      const u8 port_cap[4])  in drm_dp_set_subconnector_property()
1227 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);  in drm_dp_set_subconnector_property()
2595 			       const u8 port_cap[4])  in drm_dp_get_pcon_max_frl_bw()
2600 	buf = port_cap[2];  in drm_dp_get_pcon_max_frl_bw()