150 		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",  in drm_dp_link_train_clock_recovery_delay()
166 		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",  in __drm_dp_link_train_channel_eq_delay()
231 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",  in drm_dp_dump_access()
234 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",  in drm_dp_dump_access()
298 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",  in drm_dp_dpcd_access()
535 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",  in drm_dp_send_real_edid_checksum()
542 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",  in drm_dp_send_real_edid_checksum()
549 		drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",  in drm_dp_send_real_edid_checksum()
556 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",  in drm_dp_send_real_edid_checksum()
564 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",  in drm_dp_send_real_edid_checksum()
571 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",  in drm_dp_send_real_edid_checksum()
615 		drm_dbg_kms(aux->drm_dev,  in drm_dp_read_extended_dpcd_caps()
624 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_extended_dpcd_caps()
659 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_dpcd_caps()
708 	drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);  in drm_dp_read_downstream_info()
1425 				drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",  in drm_dp_i2c_do_msg()
1428 				drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",  in drm_dp_i2c_do_msg()
1443 			drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",  in drm_dp_i2c_do_msg()
1448 			drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);  in drm_dp_i2c_do_msg()
1462 			drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",  in drm_dp_i2c_do_msg()
1478 			drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",  in drm_dp_i2c_do_msg()
1484 			drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);  in drm_dp_i2c_do_msg()
1498 			drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",  in drm_dp_i2c_do_msg()
1504 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);  in drm_dp_i2c_do_msg()
1533 			drm_dbg_kms(aux->drm_dev,  in drm_dp_i2c_drain_msg()
1714 			drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",  in drm_dp_aux_crc_work()
1718 			drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);  in drm_dp_aux_crc_work()
1804 	WARN_ON_ONCE(!aux->drm_dev);  in drm_dp_aux_register()
2022 	drm_dbg_kms(aux->drm_dev,  in drm_dp_read_desc()
2793 		drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",  in drm_dp_pcon_frl_enable()
2889 		drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",  in drm_dp_pcon_hdmi_frl_link_error_count()
3153 		drm_err(aux->drm_dev,  in drm_edp_backlight_set_level()
3176 		drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",  in drm_edp_backlight_set_enable()
3187 		drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",  in drm_edp_backlight_set_enable()
3221 		drm_dbg_kms(aux->drm_dev,  in drm_edp_backlight_enable()
3235 				drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",  in drm_edp_backlight_enable()
3243 			drm_dbg_kms(aux->drm_dev,  in drm_edp_backlight_enable()
3253 			drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",  in drm_edp_backlight_enable()
3306 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",  in drm_edp_backlight_probe_max()
3340 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",  in drm_edp_backlight_probe_max()
3346 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",  in drm_edp_backlight_probe_max()
3357 		drm_dbg_kms(aux->drm_dev,  in drm_edp_backlight_probe_max()
3372 		drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",  in drm_edp_backlight_probe_max()
3381 		drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",  in drm_edp_backlight_probe_max()
3398 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",  in drm_edp_backlight_probe_level()
3409 			drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",  in drm_edp_backlight_probe_level()
3466 	drm_dbg_kms(aux->drm_dev,  in drm_edp_backlight_init()
3469 	drm_dbg_kms(aux->drm_dev,  in drm_edp_backlight_init()