Lines Matching +full:5 +full:gbit
141 #define CBR_PASSNUM_AST2150 5
432 #define CBR_PASSNUM 5
433 #define CBR_PASSNUM2 5
672 dlli = ((gold_sadj[0] - dlli) * 19) >> 5; in finetuneDQI_L()
677 dlli = ((dlli - gold_sadj[0]) * 19) >> 5; in finetuneDQI_L()
694 dlli = ((gold_sadj[1] - dlli) * 19) >> 5; in finetuneDQI_L()
701 dlli = ((dlli - gold_sadj[1]) * 19) >> 5; in finetuneDQI_L()
758 } else if (passcnt[dqsip] >= 5) in finetuneDQSI()
1158 data2 = ((data2 & 0xff) >> 2) + 5; in ddr3_init()
1527 data2 = ((data2 & 0xff) >> 2) + 5; in ddr2_init()
1779 /* Check 8Gbit */ in check_dram_size_2500()
1783 /* Check 4Gbit */ in check_dram_size_2500()
1787 /* Check 2Gbit */ in check_dram_size_2500()
2006 u32 max_tries = 5; in ast_dram_init_2500()
2048 * [6:5]:= 01:Full chip in ast_patch_ahb_2500()
2082 * SCU90 is Multi-function Pin Control #5 in ast_post_chip_2500()