Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
234 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
235 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
244 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
447 uint8_t h_border;
448 uint8_t v_border;
450 uint8_t atom_mode_id;
451 uint8_t refreshrate;
490 uint8_t mem_module_id;
491 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
492 uint8_t reserved1[2];
529 uint8_t mem_module_id;
530 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
531 uint8_t reserved1[2];
534 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
535 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
536 uint8_t board_i2c_feature_slave_addr;
537 uint8_t reserved3;
557 uint8_t mem_module_id;
558 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
559 uint8_t reserved1[2];
562 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
563 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
564 uint8_t board_i2c_feature_slave_addr;
565 uint8_t reserved3;
585 uint8_t mem_module_id;
586 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
587 uint8_t reserved1[2];
590 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
591 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
592 uint8_t board_i2c_feature_slave_addr;
593 uint8_t ras_rom_i2c_slave_addr;
628 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
629 uint8_t pwr_on_de_to_vary_bl;
630 uint8_t pwr_down_vary_bloff_to_de;
631 uint8_t pwr_down_de_to_digoff;
632 uint8_t pwr_off_delay;
633 uint8_t pwr_on_vary_bl_to_blon;
634 uint8_t pwr_down_bloff_to_vary_bloff;
635 uint8_t panel_bpc;
636 uint8_t dpcd_edp_config_cap;
637 uint8_t dpcd_max_link_rate;
638 uint8_t dpcd_max_lane_count;
639 uint8_t dpcd_max_downspread;
640 uint8_t min_allowed_bl_level;
641 uint8_t max_allowed_bl_level;
642 uint8_t bootup_bl_level;
643 uint8_t dplvdsrxid;
670 uint8_t gpio_bitshift;
671 uint8_t gpio_mask_bitshift;
672 uint8_t gpio_id;
673 uint8_t reserved;
745 uint8_t record_type; //An emun to indicate the record type
746 uint8_t record_size; //The size of the whole record in byte
752 uint8_t i2c_id;
753 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
759 …uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info …
760 uint8_t plugin_pin_state;
795 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
796 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
802 uint8_t flag; // Future expnadibility
803 uint8_t number_of_pins; // Number of GPIO pins used to control the object
841 uint8_t hpd_pin_map[8];
847 uint8_t aux_ddc_map[8];
854 uint8_t maxtmdsclkrate_in2_5mhz;
855 uint8_t reserved;
861 uint8_t connector_type;
862 uint8_t position;
878 uint8_t bracketlen;
879 uint8_t bracketwidth;
880 uint8_t conn_num;
881 uint8_t reserved;
906 uint8_t priority_id;
907 uint8_t reserved;
914 uint8_t number_of_path;
915 uint8_t reserved;
938 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
939 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
940 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
941 uint8_t ss_reserved;
942 …uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable wh…
943 uint8_t reserved1[3];
946 uint8_t dceip_min_ver;
947 uint8_t dceip_max_ver;
948 uint8_t max_disp_pipe_num;
949 uint8_t max_vbios_active_disp_pipe_num;
950 uint8_t max_ppll_num;
951 uint8_t max_disp_phy_num;
952 uint8_t max_aux_pairs;
953 uint8_t remotedisplayconfig;
954 uint8_t reserved3[8];
970 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
971 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
972 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
973 uint8_t ss_reserved;
974 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
975 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
976 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
977 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
980 uint8_t dcnip_min_ver;
981 uint8_t dcnip_max_ver;
982 uint8_t max_disp_pipe_num;
983 uint8_t max_vbios_active_disp_pipe_num;
984 uint8_t max_ppll_num;
985 uint8_t max_disp_phy_num;
986 uint8_t max_aux_pairs;
987 uint8_t remotedisplayconfig;
988 uint8_t reserved3[8];
1004 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1005 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1006 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1007 uint8_t ss_reserved;
1008 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
1009 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
1010 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
1011 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
1014 uint8_t dcnip_min_ver;
1015 uint8_t dcnip_max_ver;
1016 uint8_t max_disp_pipe_num;
1017 uint8_t max_vbios_active_disp_pipe_num;
1018 uint8_t max_ppll_num;
1019 uint8_t max_disp_phy_num;
1020 uint8_t max_aux_pairs;
1021 uint8_t remotedisplayconfig;
1022 uint8_t reserved3[8];
1037 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1038 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1039 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1040 uint8_t ss_reserved;
1041 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable wh…
1042 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTa…
1043 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable wh…
1044 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable w…
1047 uint8_t dcnip_min_ver;
1048 uint8_t dcnip_max_ver;
1049 uint8_t max_disp_pipe_num;
1050 uint8_t max_vbios_active_disp_pipum;
1051 uint8_t max_ppll_num;
1052 uint8_t max_disp_phy_num;
1053 uint8_t max_aux_pairs;
1054 uint8_t remotedisplayconfig;
1102 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1103 uint8_t hpdlut_index; //An index into external HPD pin LUT
1105 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
1106 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
1124 …uint8_t guid[16]; // a GUID is a 16 byte long st…
1126 …uint8_t checksum; // a simple Checksum of the su…
1127 uint8_t stereopinid; // use for eDP panel
1128 uint8_t remotedisplayconfig;
1129 uint8_t edptolvdsrxid;
1130 …uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate …
1131 uint8_t reserved[3]; // for potential expansion
1142 uint8_t profile_id; // SENSOR_PROFILES
1153 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1154 uint8_t module_name[8];
1160 uint8_t flashlight_id; // 0: Rear, 1: Front
1161 uint8_t name[8];
1177 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1178 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1180 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1181 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1182 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1183 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1187 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1189 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1190 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1194 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1195 uint8_t version;
1210 uint8_t sym_clk;
1211 uint8_t dig_mode;
1212 uint8_t phy_sel;
1214 uint8_t common_seldeemph60__deemph_6db_4_val;
1215 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1216 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1217 uint8_t margin_deemph_lane0__deemph_sel_val;
1223 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1224 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1225 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1226 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1227 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1228 uint8_t reserved1;
1229 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1230 uint8_t reserved2;
1234 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1235 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1236 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1237 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1238 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1242 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1243 uint8_t version;
1250 uint8_t ucI2cRegIndex;
1251 uint8_t ucI2cRegVal;
1255 uint8_t HdmiSlvAddr;
1256 uint8_t HdmiRegNum;
1257 uint8_t Hdmi6GRegNum;
1280 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1281 uint8_t umachannelnumber; // number of memory channels
1282 …uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1283 uint8_t pwr_on_de_to_vary_bl;
1284 uint8_t pwr_down_vary_bloff_to_de;
1285 uint8_t pwr_down_de_to_digoff;
1286 uint8_t pwr_off_delay;
1287 uint8_t pwr_on_vary_bl_to_blon;
1288 uint8_t pwr_down_bloff_to_vary_bloff;
1289 uint8_t min_allowed_bl_level;
1290 uint8_t htc_hyst_limit;
1291 uint8_t htc_tmp_limit;
1292 uint8_t reserved1;
1293 uint8_t reserved2;
1329 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1330 uint8_t umachannelnumber; // number of memory channels
1331 …uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1332 uint8_t pwr_on_de_to_vary_bl;
1333 uint8_t pwr_down_vary_bloff_to_de;
1334 uint8_t pwr_down_de_to_digoff;
1335 uint8_t pwr_off_delay;
1336 uint8_t pwr_on_vary_bl_to_blon;
1337 uint8_t pwr_down_bloff_to_vary_bloff;
1338 uint8_t min_allowed_bl_level;
1339 uint8_t htc_hyst_limit;
1340 uint8_t htc_tmp_limit;
1341 uint8_t reserved1;
1342 uint8_t reserved2;
1368 uint8_t edp_pwr_on_off_delay;
1369 uint8_t edp_pwr_on_vary_bl_to_blon;
1370 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1371 uint8_t edp_panel_bpc;
1372 uint8_t edp_bootup_bl_level;
1373 uint8_t reserved3[3];
1387 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1388 uint8_t umachannelnumber; // number of memory channels
1389 uint8_t htc_hyst_limit;
1390 uint8_t htc_tmp_limit;
1391 uint8_t reserved1;
1392 uint8_t reserved2;
1418 uint8_t display_signal_type;
1419 uint8_t phy_sel;
1420 uint8_t preset_level;
1421 uint8_t reserved1;
1424 uint8_t tx_vboost_level;
1425 uint8_t tx_vreg_v2i;
1426 uint8_t tx_vregdrv_byp;
1427 uint8_t tx_term_cntl;
1428 uint8_t tx_peak_level;
1429 uint8_t tx_slew_en;
1430 uint8_t tx_eq_pre;
1431 uint8_t tx_eq_main;
1432 uint8_t tx_eq_post;
1433 uint8_t tx_en_inv_pre;
1434 uint8_t tx_en_inv_post;
1435 uint8_t reserved3;
1456 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1457 uint8_t umachannelnumber; // number of memory channels
1458 uint8_t htc_hyst_limit;
1459 uint8_t htc_tmp_limit;
1460 uint8_t reserved1;
1461 uint8_t reserved2;
1553 uint8_t gfxip_min_ver;
1554 uint8_t gfxip_max_ver;
1555 uint8_t max_shader_engines;
1556 uint8_t max_tile_pipes;
1557 uint8_t max_cu_per_sh;
1558 uint8_t max_sh_per_se;
1559 uint8_t max_backends_per_se;
1560 uint8_t max_texture_channel_caches;
1573 uint8_t gfxip_min_ver;
1574 uint8_t gfxip_max_ver;
1575 uint8_t max_shader_engines;
1576 uint8_t max_tile_pipes;
1577 uint8_t max_cu_per_sh;
1578 uint8_t max_sh_per_se;
1579 uint8_t max_backends_per_se;
1580 uint8_t max_texture_channel_caches;
1589 uint8_t active_cu_per_sh;
1590 uint8_t active_rb_per_se;
1598 uint8_t gfxip_min_ver;
1599 uint8_t gfxip_max_ver;
1600 uint8_t max_shader_engines;
1601 uint8_t reserved;
1602 uint8_t max_cu_per_sh;
1603 uint8_t max_sh_per_se;
1604 uint8_t max_backends_per_se;
1605 uint8_t max_texture_channel_caches;
1614 uint8_t active_cu_per_sh;
1615 uint8_t active_rb_per_se;
1623 uint8_t gc_num_max_gs_thds;
1624 uint8_t gc_gs_table_depth;
1625 uint8_t gc_double_offchip_lds_buffer;
1626 uint8_t gc_max_scratch_slots_per_cu;
1633 uint8_t gfxip_min_ver;
1634 uint8_t gfxip_max_ver;
1635 uint8_t max_shader_engines;
1636 uint8_t reserved;
1637 uint8_t max_cu_per_sh;
1638 uint8_t max_sh_per_se;
1639 uint8_t max_backends_per_se;
1640 uint8_t max_texture_channel_caches;
1649 uint8_t active_cu_per_sh;
1650 uint8_t active_rb_per_se;
1658 uint8_t gc_num_max_gs_thds;
1659 uint8_t gc_gs_table_depth;
1660 uint8_t gc_double_offchip_lds_buffer;
1661 uint8_t gc_max_scratch_slots_per_cu;
1664 uint8_t cut_cu;
1665 uint8_t active_cu_total;
1666 uint8_t cu_reserved[2];
1668 uint8_t inactive_cu_per_se[8];
1680 uint8_t smuip_min_ver;
1681 uint8_t smuip_max_ver;
1682 uint8_t smu_rsd1;
1683 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1689 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1690 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1691 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1692 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1693 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1694 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1695 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1696 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1701 uint8_t smuip_min_ver;
1702 uint8_t smuip_max_ver;
1703 uint8_t smu_rsd1;
1704 uint8_t gpuclk_ss_mode;
1710 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1711 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1712 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1713 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1714 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1715 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1716 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1717 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1718 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1719 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1734 uint8_t smuip_min_ver;
1735 uint8_t smuip_max_ver;
1736 uint8_t waflclk_ss_mode;
1737 uint8_t gpuclk_ss_mode;
1743 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1744 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1745 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1746 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1747 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1748 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1749 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1750 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1751 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1752 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1780 uint8_t liquid1_i2c_address;
1781 uint8_t liquid2_i2c_address;
1782 uint8_t vr_i2c_address;
1783 uint8_t plx_i2c_address;
1785 uint8_t liquid_i2c_linescl;
1786 uint8_t liquid_i2c_linesda;
1787 uint8_t vr_i2c_linescl;
1788 uint8_t vr_i2c_linesda;
1790 uint8_t plx_i2c_linescl;
1791 uint8_t plx_i2c_linesda;
1792 uint8_t vrsensorpresent;
1793 uint8_t liquidsensorpresent;
1798 uint8_t vddgfxvrmapping;
1799 uint8_t vddsocvrmapping;
1800 uint8_t vddmem0vrmapping;
1801 uint8_t vddmem1vrmapping;
1803 uint8_t gfxulvphasesheddingmask;
1804 uint8_t soculvphasesheddingmask;
1805 uint8_t padding8_v[2];
1808 uint8_t gfxoffset;
1809 uint8_t padding_telemetrygfx;
1812 uint8_t socoffset;
1813 uint8_t padding_telemetrysoc;
1816 uint8_t mem0offset;
1817 uint8_t padding_telemetrymem0;
1820 uint8_t mem1offset;
1821 uint8_t padding_telemetrymem1;
1823 uint8_t acdcgpio;
1824 uint8_t acdcpolarity;
1825 uint8_t vr0hotgpio;
1826 uint8_t vr0hotpolarity;
1828 uint8_t vr1hotgpio;
1829 uint8_t vr1hotpolarity;
1830 uint8_t padding1;
1831 uint8_t padding2;
1833 uint8_t ledpin0;
1834 uint8_t ledpin1;
1835 uint8_t ledpin2;
1836 uint8_t padding8_4;
1838 uint8_t pllgfxclkspreadenabled;
1839 uint8_t pllgfxclkspreadpercent;
1842 uint8_t uclkspreadenabled;
1843 uint8_t uclkspreadpercent;
1846 uint8_t socclkspreadenabled;
1847 uint8_t socclkspreadpercent;
1850 uint8_t acggfxclkspreadenabled;
1851 uint8_t acggfxclkspreadpercent;
1854 uint8_t Vr2_I2C_address;
1855 uint8_t padding_vr2[3];
1868 uint8_t liquid1_i2c_address;
1869 uint8_t liquid2_i2c_address;
1870 uint8_t vr_i2c_address;
1871 uint8_t plx_i2c_address;
1873 uint8_t liquid_i2c_linescl;
1874 uint8_t liquid_i2c_linesda;
1875 uint8_t vr_i2c_linescl;
1876 uint8_t vr_i2c_linesda;
1878 uint8_t plx_i2c_linescl;
1879 uint8_t plx_i2c_linesda;
1880 uint8_t vrsensorpresent;
1881 uint8_t liquidsensorpresent;
1886 uint8_t vddgfxvrmapping;
1887 uint8_t vddsocvrmapping;
1888 uint8_t vddmem0vrmapping;
1889 uint8_t vddmem1vrmapping;
1891 uint8_t gfxulvphasesheddingmask;
1892 uint8_t soculvphasesheddingmask;
1893 uint8_t externalsensorpresent;
1894 uint8_t padding8_v;
1897 uint8_t gfxoffset;
1898 uint8_t padding_telemetrygfx;
1901 uint8_t socoffset;
1902 uint8_t padding_telemetrysoc;
1905 uint8_t mem0offset;
1906 uint8_t padding_telemetrymem0;
1909 uint8_t mem1offset;
1910 uint8_t padding_telemetrymem1;
1912 uint8_t acdcgpio;
1913 uint8_t acdcpolarity;
1914 uint8_t vr0hotgpio;
1915 uint8_t vr0hotpolarity;
1917 uint8_t vr1hotgpio;
1918 uint8_t vr1hotpolarity;
1919 uint8_t padding1;
1920 uint8_t padding2;
1922 uint8_t ledpin0;
1923 uint8_t ledpin1;
1924 uint8_t ledpin2;
1925 uint8_t padding8_4;
1927 uint8_t pllgfxclkspreadenabled;
1928 uint8_t pllgfxclkspreadpercent;
1931 uint8_t uclkspreadenabled;
1932 uint8_t uclkspreadpercent;
1935 uint8_t fclkspreadenabled;
1936 uint8_t fclkspreadpercent;
1939 uint8_t fllgfxclkspreadenabled;
1940 uint8_t fllgfxclkspreadpercent;
1964 uint8_t vddgfxvrmapping;
1965 uint8_t vddsocvrmapping;
1966 uint8_t vddmem0vrmapping;
1967 uint8_t vddmem1vrmapping;
1969 uint8_t gfxulvphasesheddingmask;
1970 uint8_t soculvphasesheddingmask;
1971 uint8_t externalsensorpresent;
1972 uint8_t padding8_v;
1975 uint8_t gfxoffset;
1976 uint8_t padding_telemetrygfx;
1979 uint8_t socoffset;
1980 uint8_t padding_telemetrysoc;
1983 uint8_t mem0offset;
1984 uint8_t padding_telemetrymem0;
1987 uint8_t mem1offset;
1988 uint8_t padding_telemetrymem1;
1991 uint8_t acdcgpio;
1992 uint8_t acdcpolarity;
1993 uint8_t vr0hotgpio;
1994 uint8_t vr0hotpolarity;
1996 uint8_t vr1hotgpio;
1997 uint8_t vr1hotpolarity;
1998 uint8_t padding1;
1999 uint8_t padding2;
2002 uint8_t ledpin0;
2003 uint8_t ledpin1;
2004 uint8_t ledpin2;
2005 uint8_t padding8_4;
2008 uint8_t pllgfxclkspreadenabled;
2009 uint8_t pllgfxclkspreadpercent;
2013 uint8_t uclkspreadenabled;
2014 uint8_t uclkspreadpercent;
2018 uint8_t fclkspreadenabled;
2019 uint8_t fclkspreadpercent;
2023 uint8_t fllgfxclkspreadenabled;
2024 uint8_t fllgfxclkspreadpercent;
2070 uint8_t Enabled;
2071 uint8_t Speed;
2072 uint8_t Padding[2];
2074 uint8_t ControllerPort;
2075 uint8_t ControllerName;
2076 uint8_t ThermalThrotter;
2077 uint8_t I2cProtocol;
2091 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2092 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2093 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2094 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2096 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2097 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2098 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2099 uint8_t Padding8_V;
2103 uint8_t GfxOffset; // in Amps
2104 uint8_t Padding_TelemetryGfx;
2106 uint8_t SocOffset; // in Amps
2107 uint8_t Padding_TelemetrySoc;
2110 uint8_t Mem0Offset; // in Amps
2111 uint8_t Padding_TelemetryMem0;
2114 uint8_t Mem1Offset; // in Amps
2115 uint8_t Padding_TelemetryMem1;
2118 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2119 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2120 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2121 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2123 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2124 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2125 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2126 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2129 uint8_t LedPin0; // GPIO number for LedPin[0]
2130 uint8_t LedPin1; // GPIO number for LedPin[1]
2131 uint8_t LedPin2; // GPIO number for LedPin[2]
2132 uint8_t padding8_4;
2135 uint8_t PllGfxclkSpreadEnabled; // on or off
2136 uint8_t PllGfxclkSpreadPercent; // Q4.4
2140 uint8_t DfllGfxclkSpreadEnabled; // on or off
2141 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2145 uint8_t UclkSpreadEnabled; // on or off
2146 uint8_t UclkSpreadPercent; // Q4.4
2150 uint8_t SoclkSpreadEnabled; // on or off
2151 uint8_t SocclkSpreadPercent; // Q4.4
2174 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2175 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2176 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2177 uint8_t boardvrmapping; // use vr_mapping* bitfields
2179 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2180 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2181 uint8_t padding8_v[2];
2185 uint8_t gfxoffset; // in amps
2186 uint8_t padding_telemetrygfx;
2189 uint8_t socoffset; // in amps
2190 uint8_t padding_telemetrysoc;
2193 uint8_t memoffset; // in amps
2194 uint8_t padding_telemetrymem;
2197 uint8_t boardoffset; // in amps
2198 uint8_t padding_telemetryboardinput;
2201 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2202 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2203 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2204 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2207 uint8_t pllgfxclkspreadenabled; // on or off
2208 uint8_t pllgfxclkspreadpercent; // q4.4
2212 uint8_t uclkspreadenabled; // on or off
2213 uint8_t uclkspreadpercent; // q4.4
2217 uint8_t fclkspreadenabled; // on or off
2218 uint8_t fclkspreadpercent; // q4.4
2223 uint8_t fllgfxclkspreadenabled; // on or off
2224 uint8_t fllgfxclkspreadpercent; // q4.4
2233 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2234 uint8_t paddingmem[3];
2241 uint8_t xgmilinkspeed[4];
2242 uint8_t xgmilinkwidth[4];
2262 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2263 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2264 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2265 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2267 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2268 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2269 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2270 uint8_t Padding8_V;
2274 uint8_t GfxOffset; // in Amps
2275 uint8_t Padding_TelemetryGfx;
2277 uint8_t SocOffset; // in Amps
2278 uint8_t Padding_TelemetrySoc;
2281 uint8_t Mem0Offset; // in Amps
2282 uint8_t Padding_TelemetryMem0;
2285 uint8_t Mem1Offset; // in Amps
2286 uint8_t Padding_TelemetryMem1;
2289 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2290 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2291 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2292 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2294 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2295 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2296 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2297 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2300 uint8_t LedPin0; // GPIO number for LedPin[0]
2301 uint8_t LedPin1; // GPIO number for LedPin[1]
2302 uint8_t LedPin2; // GPIO number for LedPin[2]
2303 uint8_t padding8_4;
2306 uint8_t PllGfxclkSpreadEnabled; // on or off
2307 uint8_t PllGfxclkSpreadPercent; // Q4.4
2311 uint8_t DfllGfxclkSpreadEnabled; // on or off
2312 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2316 uint8_t UclkSpreadEnabled; // on or off
2317 uint8_t UclkSpreadPercent; // Q4.4
2321 uint8_t SoclkSpreadEnabled; // on or off
2322 uint8_t SocclkSpreadPercent; // Q4.4
2333 uint8_t GpioI2cScl; // Serial Clock
2334 uint8_t GpioI2cSda; // Serial Data
2338 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2339 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2343 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2345 uint8_t MvddUlvPhaseSheddingMask;
2346 uint8_t VddciUlvPhaseSheddingMask;
2347 uint8_t Padding8_Psi1;
2348 uint8_t Padding8_Psi2;
2355 uint8_t Enabled;
2356 uint8_t Speed;
2357 uint8_t SlaveAddress;
2358 uint8_t ControllerPort;
2359 uint8_t ControllerName;
2360 uint8_t ThermalThrotter;
2361 uint8_t I2cProtocol;
2362 uint8_t PaddingConfig;
2375 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2376 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2377 …uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when enter…
2378 uint8_t I2cSpare;
2381 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2382 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2383 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2384 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2386 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2387 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2388 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2389 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2393 uint8_t GfxOffset; // in Amps
2394 uint8_t Padding_TelemetryGfx;
2397 uint8_t SocOffset; // in Amps
2398 uint8_t Padding_TelemetrySoc;
2401 uint8_t Mem0Offset; // in Amps
2402 uint8_t Padding_TelemetryMem0;
2405 uint8_t Mem1Offset; // in Amps
2406 uint8_t Padding_TelemetryMem1;
2411 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2412 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2413 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2414 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2416 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2417 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2418 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2419 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2422 uint8_t LedPin0; // GPIO number for LedPin[0]
2423 uint8_t LedPin1; // GPIO number for LedPin[1]
2424 uint8_t LedPin2; // GPIO number for LedPin[2]
2425 uint8_t LedEnableMask;
2427 uint8_t LedPcie; // GPIO number for PCIE results
2428 uint8_t LedError; // GPIO number for Error Cases
2429 uint8_t LedSpare1[2];
2434 uint8_t PllGfxclkSpreadEnabled; // on or off
2435 uint8_t PllGfxclkSpreadPercent; // Q4.4
2439 uint8_t DfllGfxclkSpreadEnabled; // on or off
2440 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2444 uint8_t UclkSpreadEnabled; // on or off
2445 uint8_t UclkSpreadPercent; // Q4.4
2449 uint8_t FclkSpreadEnabled; // on or off
2450 uint8_t FclkSpreadPercent; // Q4.4
2456 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2457 uint8_t PaddingMem1[3];
2464 uint8_t XgmiLinkSpeed [4];
2465 uint8_t XgmiLinkWidth [4];
2483 uint8_t GfxOffset; // in Amps
2484 uint8_t Padding_TelemetryGfx;
2487 uint8_t SocOffset; // in Amps
2488 uint8_t Padding_TelemetrySoc;
2491 uint8_t MemOffset; // in Amps
2492 uint8_t Padding_TelemetryMem;
2495 uint8_t BoardOffset; // in Amps
2496 uint8_t Padding_TelemetryBoardInput;
2503 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2504 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2505 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2506 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2509 uint8_t UclkSpreadEnabled; // on or off
2510 uint8_t UclkSpreadPercent; // Q4.4
2514 uint8_t FclkSpreadEnabled; // on or off
2515 uint8_t FclkSpreadPercent; // Q4.4
2522 uint8_t GpioI2cScl; // Serial Clock
2523 uint8_t GpioI2cSda; // Serial Data
2558 uint8_t enable_gb_vdroop_table_cksoff;
2559 uint8_t enable_gb_vdroop_table_ckson;
2560 uint8_t enable_gb_fuse_table_cksoff;
2561 uint8_t enable_gb_fuse_table_ckson;
2563 uint8_t enable_apply_avfs_cksoff_voltage;
2564 uint8_t reserved;
2602 uint8_t enable_gb_vdroop_table_cksoff;
2603 uint8_t enable_gb_vdroop_table_ckson;
2604 uint8_t enable_gb_fuse_table_cksoff;
2605 uint8_t enable_gb_fuse_table_ckson;
2607 uint8_t enable_apply_avfs_cksoff_voltage;
2608 uint8_t reserved;
2627 uint8_t enable_acg_gb_vdroop_table;
2628 uint8_t enable_acg_gb_fuse_table;
2651 uint8_t uvdip_min_ver;
2652 uint8_t uvdip_max_ver;
2653 uint8_t vceip_min_ver;
2654 uint8_t vceip_max_ver;
2679 uint8_t umcip_min_ver;
2680 uint8_t umcip_max_ver;
2681 uint8_t vram_type; //enum of atom_dgpu_vram_type
2682 uint8_t umc_config;
2706 uint8_t umcip_min_ver;
2707 uint8_t umcip_max_ver;
2708 uint8_t vram_type; //enum of atom_dgpu_vram_type
2709 uint8_t umc_config;
2726 uint8_t umcip_min_ver;
2727 uint8_t umcip_max_ver;
2728 uint8_t vram_type; //enum of atom_dgpu_vram_type
2729 uint8_t umc_config;
2761 uint8_t ext_memory_id; // Current memory module ID
2762 uint8_t memory_type; // enum of atom_dgpu_vram_type
2763 uint8_t channel_num; // Number of mem. channels supported in this module
2764 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2765 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2766 uint8_t tunningset_id; // MC phy registers set per.
2767 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2768 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2769 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2770 uint8_t vram_rsd2; // reserved
2784 uint8_t vram_module_num; // indicate number of VRAM module
2785 uint8_t umcip_min_ver;
2786 uint8_t umcip_max_ver;
2787 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2839 uint8_t ext_memory_id; // Current memory module ID
2840 uint8_t memory_type; // enum of atom_dgpu_vram_type
2841 uint8_t channel_num; // Number of mem. channels supported in this module
2842 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2843 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2844 uint8_t tunningset_id; // MC phy registers set per
2845 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2846 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2847 uint8_t vram_flags; // bit0= bankgroup enable
2848 uint8_t vram_rsd2; // reserved
2866 uint8_t vram_module_num; // indicate number of VRAM module
2867 uint8_t umcip_min_ver;
2868 uint8_t umcip_max_ver;
2869 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2879 uint8_t ext_memory_id; // Current memory module ID
2880 uint8_t memory_type; // enum of atom_dgpu_vram_type
2881 uint8_t channel_num; // Number of mem. channels supported in this module
2882 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2883 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2884 uint8_t tunningset_id; // MC phy registers set per.
2886 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2887 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2888 uint8_t vram_flags; // bit0= bankgroup enable
2889 uint8_t vram_rsd2; // reserved
2902 uint8_t RL;
2903 uint8_t WL;
2904 uint8_t tRAS;
2905 uint8_t tRC;
2908 uint8_t tRFC;
2909 uint8_t tRFCpb;
2911 uint8_t tRREFD;
2912 uint8_t tRCDRD;
2913 uint8_t tRCDWR;
2914 uint8_t tRP;
2916 uint8_t tRRDS;
2917 uint8_t tRRDL;
2918 uint8_t tWR;
2919 uint8_t tWTRS;
2921 uint8_t tWTRL;
2922 uint8_t tFAW;
2923 uint8_t tCCDS;
2924 uint8_t tCCDL;
2926 uint8_t tCRCRL;
2927 uint8_t tCRCWL;
2928 uint8_t tCKE;
2929 uint8_t tCKSRE;
2931 uint8_t tCKSRX;
2932 uint8_t tRTPS;
2933 uint8_t tRTPL;
2934 uint8_t tMRD;
2936 uint8_t tMOD;
2937 uint8_t tXS;
2938 uint8_t tXHP;
2939 uint8_t tXSMRS;
2943 uint8_t tPD;
2944 uint8_t tXP;
2945 uint8_t tCPDED;
2946 uint8_t tACTPDE;
2948 uint8_t tPREPDE;
2949 uint8_t tREFPDE;
2950 uint8_t tMRSPDEN;
2951 uint8_t tRDSRE;
2953 uint8_t tWRSRE;
2954 uint8_t tPPD;
2955 uint8_t tCCDMW;
2956 uint8_t tWTRTR;
2958 uint8_t tLTLTR;
2959 uint8_t tREFTR;
2960 uint8_t VNDR;
2961 uint8_t reserved[9];
2976 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
2990 uint8_t vram_module_num; // indicate number of VRAM module
2991 uint8_t umcip_min_ver;
2992 uint8_t umcip_max_ver;
2993 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
3007 uint8_t vram_module_num;
3008 uint8_t umcip_min_ver;
3009 uint8_t umcip_max_ver;
3010 uint8_t mc_phy_tile_num;
3025 uint8_t voltage_type; //enum atom_voltage_type
3026 uint8_t voltage_mode; //enum atom_voltage_object_mode
3044 uint8_t regulator_id; //Indicate Voltage Regulator Id
3045 uint8_t i2c_id;
3046 uint8_t i2c_slave_addr;
3047 uint8_t i2c_control_offset;
3048 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3049 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
3050 uint8_t reserved[2];
3071 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
3072 …uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value L…
3073 uint8_t phase_delay_us; // phase delay in unit of micro second
3074 uint8_t reserved;
3082 …uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and…
3083 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3084 uint8_t psi0_enable; //
3085 uint8_t maxvstep;
3086 uint8_t telemetry_offset;
3087 uint8_t telemetry_gain;
3094 uint8_t merged_powerrail_type; //enum atom_voltage_type
3095 uint8_t reserved[3];
3240 uint8_t voltagetype; /* enum atom_voltage_type */
3241 …uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_…
3289 uint8_t pll_ss_enable;
3290 uint8_t reserved;
3305 uint8_t reserved;
3306 uint8_t bitslen;
3324 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3325 …uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLO…
3326 uint8_t command; // enum of atom_get_smu_clock_info_command
3327 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
3505 uint8_t ucode_func_id;
3506 uint8_t ucode_reserved[3];
3521 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3522 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
3524 uint8_t encoder_mode; // Encoder mode:
3525 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
3526 uint8_t crtc_id; // enum of atom_crtc_def
3527 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
3528 uint8_t reserved1[2];
3567 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
3568 …uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK …
3569 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
3570 …uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use on…
3614 uint8_t crtc_id; // enum atom_crtc_def
3615 uint8_t blanking; // enum atom_blank_crtc_command
3631 uint8_t crtc_id; // enum atom_crtc_def
3632 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3633 uint8_t padding[2];
3642 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
3643 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3644 uint8_t padding[2];
3667 uint8_t h_border;
3668 uint8_t v_border;
3669 uint8_t crtc_id; // enum atom_crtc_def
3670 uint8_t encoder_mode; // atom_encode_mode_def
3671 uint8_t padding[2];
3680 uint8_t i2cspeed_khz;
3682 uint8_t regindex;
3683 uint8_t status; /* enum atom_process_i2c_flag */
3686 uint8_t flag; /* enum atom_process_i2c_status */
3687 uint8_t trans_bytes;
3688 uint8_t slave_addr;
3689 uint8_t i2c_id;
3717 uint8_t channelid;
3719 uint8_t reply_status;
3720 uint8_t aux_delay;
3722 uint8_t dataout_len;
3723 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
3733 uint8_t crtc_id; // enum atom_crtc_def
3734 uint8_t encoder_id; // enum atom_dig_def
3735 uint8_t encode_mode; // enum atom_encode_mode_def
3736 uint8_t dst_bpc; // enum atom_panel_bit_per_color
3786 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3787 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
3788 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3789 uint8_t lanenum; // Lane number
3791 uint8_t bitpercolor;
3792 …uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz…
3793 uint8_t reserved[2];
3798 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3799 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
3800 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3801 uint8_t lanenum; // Lane number
3802 uint8_t symclk_10khz; // Symbol Clock in 10Khz
3803 uint8_t hpd_sel;
3804 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3805 uint8_t reserved[2];
3810 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3811 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
3812 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
3813 uint8_t reserved1;
3819 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3820 uint8_t action; // = rest of generic encoder command which does not carry any parameters
3821 uint8_t reserved1[2];
3840 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3841 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3843 uint8_t digmode; // enum atom_encode_mode_def
3844 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
3846 uint8_t lanenum; // Lane number 1, 2, 4, 8
3848 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3849 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3850 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3851 uint8_t reserved;
3929 …uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENAB…
3930 uint8_t action; //
3931 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3932 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3933 …uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPU…
3934 uint8_t hpd_id;
3982 uint8_t revision;
3983 uint8_t checksum;
3984 uint8_t oemId[6];
3985 uint8_t oemTableId[8]; //UINT64 OemTableId;
3993 uint8_t tableUUID[16]; //0x24
4014 uint8_t vbioscontent[1];
4019 uint8_t lib1content[1];