440 		return sysfs_show_str_val(buffer, offs, dev->node_props.name);  in node_show()
448 			      dev->node_props.cpu_cores_count);  in node_show()
450 			      dev->gpu ? dev->node_props.simd_count : 0);  in node_show()
452 			      dev->node_props.mem_banks_count);  in node_show()
454 			      dev->node_props.caches_count);  in node_show()
456 			      dev->node_props.io_links_count);  in node_show()
458 			      dev->node_props.cpu_core_id_base);  in node_show()
460 			      dev->node_props.simd_id_base);  in node_show()
462 			      dev->node_props.max_waves_per_simd);  in node_show()
464 			      dev->node_props.lds_size_in_kb);  in node_show()
466 			      dev->node_props.gds_size_in_kb);  in node_show()
468 			      dev->node_props.num_gws);  in node_show()
470 			      dev->node_props.wave_front_size);  in node_show()
472 			      dev->node_props.array_count);  in node_show()
474 			      dev->node_props.simd_arrays_per_engine);  in node_show()
476 			      dev->node_props.cu_per_simd_array);  in node_show()
478 			      dev->node_props.simd_per_cu);  in node_show()
480 			      dev->node_props.max_slots_scratch_cu);  in node_show()
482 			      dev->node_props.gfx_target_version);  in node_show()
484 			      dev->node_props.vendor_id);  in node_show()
486 			      dev->node_props.device_id);  in node_show()
488 			      dev->node_props.location_id);  in node_show()
490 			      dev->node_props.domain);  in node_show()
492 			      dev->node_props.drm_render_minor);  in node_show()
494 			      dev->node_props.hive_id);  in node_show()
496 			      dev->node_props.num_sdma_engines);  in node_show()
498 			      dev->node_props.num_sdma_xgmi_engines);  in node_show()
500 			      dev->node_props.num_sdma_queues_per_engine);  in node_show()
502 			      dev->node_props.num_cp_queues);  in node_show()
509 			dev->node_props.capability |=  in node_show()
512 			dev->node_props.capability |=  in node_show()
519 			dev->node_props.capability |=  in node_show()
523 			dev->node_props.max_engine_clk_fcompute);  in node_show()
530 				      dev->node_props.capability);  in node_show()
887 		if (dev->node_props.cpu_cores_count &&  in kfd_debug_print_topology()
888 				dev->node_props.simd_count) {  in kfd_debug_print_topology()
890 				dev->node_props.device_id,  in kfd_debug_print_topology()
891 				dev->node_props.vendor_id);  in kfd_debug_print_topology()
892 		} else if (dev->node_props.cpu_cores_count)  in kfd_debug_print_topology()
894 		else if (dev->node_props.simd_count)  in kfd_debug_print_topology()
896 				dev->node_props.device_id,  in kfd_debug_print_topology()
897 				dev->node_props.vendor_id);  in kfd_debug_print_topology()
978 		if (dev->node_props.cpu_cores_count &&  in kfd_is_acpi_crat_invalid()
979 			dev->node_props.simd_count)  in kfd_is_acpi_crat_invalid()
1147 		    dev->node_props.cpu_cores_count)  in kfd_assign_gpu()
1150 		if (!dev->gpu && (dev->node_props.simd_count > 0)) {  in kfd_assign_gpu()
1359 	strncpy(dev->node_props.name, gpu->device_info->asic_name,  in kfd_topology_add_device()
1362 	dev->node_props.simd_arrays_per_engine =  in kfd_topology_add_device()
1365 	dev->node_props.gfx_target_version = gpu->device_info->gfx_target_version;  in kfd_topology_add_device()
1366 	dev->node_props.vendor_id = gpu->pdev->vendor;  in kfd_topology_add_device()
1367 	dev->node_props.device_id = gpu->pdev->device;  in kfd_topology_add_device()
1368 	dev->node_props.capability |=  in kfd_topology_add_device()
1372 	dev->node_props.location_id = pci_dev_id(gpu->pdev);  in kfd_topology_add_device()
1373 	dev->node_props.domain = pci_domain_nr(gpu->pdev->bus);  in kfd_topology_add_device()
1374 	dev->node_props.max_engine_clk_fcompute =  in kfd_topology_add_device()
1376 	dev->node_props.max_engine_clk_ccompute =  in kfd_topology_add_device()
1378 	dev->node_props.drm_render_minor =  in kfd_topology_add_device()
1381 	dev->node_props.hive_id = gpu->hive_id;  in kfd_topology_add_device()
1382 	dev->node_props.num_sdma_engines = gpu->device_info->num_sdma_engines;  in kfd_topology_add_device()
1383 	dev->node_props.num_sdma_xgmi_engines =  in kfd_topology_add_device()
1385 	dev->node_props.num_sdma_queues_per_engine =  in kfd_topology_add_device()
1387 	dev->node_props.num_gws = (dev->gpu->gws &&  in kfd_topology_add_device()
1390 	dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);  in kfd_topology_add_device()
1399 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<  in kfd_topology_add_device()
1410 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<  in kfd_topology_add_device()
1431 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<  in kfd_topology_add_device()
1445 		dev->node_props.capability |= HSA_CAP_ATS_PRESENT;  in kfd_topology_add_device()
1447 		dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;  in kfd_topology_add_device()
1455 		dev->node_props.simd_count =  in kfd_topology_add_device()
1457 		dev->node_props.max_waves_per_simd = 10;  in kfd_topology_add_device()
1462 	dev->node_props.capability |=  in kfd_topology_add_device()
1465 	dev->node_props.capability |= ((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?  in kfd_topology_add_device()
1469 		dev->node_props.capability |= (adev->ras_enabled != 0) ?  in kfd_topology_add_device()
1473 		dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;  in kfd_topology_add_device()
1587 		if (dev->node_props.cpu_cores_count &&  in kfd_double_confirm_iommu_support()
1588 		    dev->node_props.simd_count &&  in kfd_double_confirm_iommu_support()