338 	struct pm4__set_config_reg *packets_vec;  in dbgdev_address_watch_diq()  local
377 	packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint);  in dbgdev_address_watch_diq()
379 	packets_vec[0].header.count = 1;  in dbgdev_address_watch_diq()
380 	packets_vec[0].header.opcode = IT_SET_CONFIG_REG;  in dbgdev_address_watch_diq()
381 	packets_vec[0].header.type = PM4_TYPE_3;  in dbgdev_address_watch_diq()
382 	packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
383 	packets_vec[0].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
384 	packets_vec[1].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
385 	packets_vec[1].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
386 	packets_vec[2].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
387 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
388 	packets_vec[3].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
389 	packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
390 	packets_vec[3].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
427 		packets_vec[0].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
430 		packets_vec[0].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
438 		packets_vec[1].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
440 		packets_vec[1].reg_data[0] = addrHi.u32All;  in dbgdev_address_watch_diq()
448 		packets_vec[2].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
450 		packets_vec[2].reg_data[0] = addrLo.u32All;  in dbgdev_address_watch_diq()
464 		packets_vec[3].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
466 		packets_vec[3].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
592 	struct pm4__set_config_reg *packets_vec;  in dbgdev_wave_control_diq()  local
648 	packets_vec =  (struct pm4__set_config_reg *) packet_buff_uint;  in dbgdev_wave_control_diq()
649 	packets_vec[0].header.count = 1;  in dbgdev_wave_control_diq()
650 	packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;  in dbgdev_wave_control_diq()
651 	packets_vec[0].header.type = PM4_TYPE_3;  in dbgdev_wave_control_diq()
652 	packets_vec[0].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
655 	packets_vec[0].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()
656 	packets_vec[0].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()
658 	packets_vec[1].header.count = 1;  in dbgdev_wave_control_diq()
659 	packets_vec[1].header.opcode = IT_SET_CONFIG_REG;  in dbgdev_wave_control_diq()
660 	packets_vec[1].header.type = PM4_TYPE_3;  in dbgdev_wave_control_diq()
661 	packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE;  in dbgdev_wave_control_diq()
663 	packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;  in dbgdev_wave_control_diq()
664 	packets_vec[1].bitfields2.insert_vmid = 1;  in dbgdev_wave_control_diq()
665 	packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;  in dbgdev_wave_control_diq()
675 	packets_vec[2].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_wave_control_diq()
676 	packets_vec[2].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
679 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()
680 	packets_vec[2].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()