93 		adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;  in vcn_v3_0_early_init()
94 		adev->vcn.harvest_config = 0;  in vcn_v3_0_early_init()
95 		adev->vcn.num_enc_rings = 1;  in vcn_v3_0_early_init()
101 			adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;  in vcn_v3_0_early_init()
102 			for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v3_0_early_init()
105 					adev->vcn.harvest_config |= 1 << i;  in vcn_v3_0_early_init()
108 			if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |  in vcn_v3_0_early_init()
113 			adev->vcn.num_vcn_inst = 1;  in vcn_v3_0_early_init()
116 			adev->vcn.num_enc_rings = 0;  in vcn_v3_0_early_init()
118 			adev->vcn.num_enc_rings = 2;  in vcn_v3_0_early_init()
148 		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;  in vcn_v3_0_sw_init()
150 		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;  in vcn_v3_0_sw_init()
154 		if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {  in vcn_v3_0_sw_init()
156 			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;  in vcn_v3_0_sw_init()
175 		vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;  in vcn_v3_0_sw_init()
180 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v3_0_sw_init()
183 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_sw_init()
186 		adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
187 		adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
188 		adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
189 		adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
190 		adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
191 		adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
193 		adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
194 		adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);  in vcn_v3_0_sw_init()
195 		adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
196 		adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v3_0_sw_init()
197 		adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
198 		adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v3_0_sw_init()
199 		adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
200 		adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);  in vcn_v3_0_sw_init()
201 		adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;  in vcn_v3_0_sw_init()
202 		adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);  in vcn_v3_0_sw_init()
206 				VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);  in vcn_v3_0_sw_init()
210 		atomic_set(&adev->vcn.inst[i].sched_score, 0);  in vcn_v3_0_sw_init()
212 		ring = &adev->vcn.inst[i].ring_dec;  in vcn_v3_0_sw_init()
215 			ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);  in vcn_v3_0_sw_init()
217 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;  in vcn_v3_0_sw_init()
220 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,  in vcn_v3_0_sw_init()
222 				     &adev->vcn.inst[i].sched_score);  in vcn_v3_0_sw_init()
226 		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {  in vcn_v3_0_sw_init()
229 				j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);  in vcn_v3_0_sw_init()
233 			ring = &adev->vcn.inst[i].ring_enc[j];  in vcn_v3_0_sw_init()
236 				ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;  in vcn_v3_0_sw_init()
238 				ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;  in vcn_v3_0_sw_init()
241 			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,  in vcn_v3_0_sw_init()
243 					     &adev->vcn.inst[i].sched_score);  in vcn_v3_0_sw_init()
248 		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;  in vcn_v3_0_sw_init()
261 		adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;  in vcn_v3_0_sw_init()
279 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v3_0_sw_fini()
282 			if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_sw_fini()
284 			fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;  in vcn_v3_0_sw_fini()
323 		for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_hw_init()
324 			if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_hw_init()
327 			ring = &adev->vcn.inst[i].ring_dec;  in vcn_v3_0_hw_init()
338 			for (j = 0; j < adev->vcn.num_enc_rings; ++j) {  in vcn_v3_0_hw_init()
339 				ring = &adev->vcn.inst[i].ring_enc[j];  in vcn_v3_0_hw_init()
352 		for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_hw_init()
353 			if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_hw_init()
356 			ring = &adev->vcn.inst[i].ring_dec;  in vcn_v3_0_hw_init()
365 			for (j = 0; j < adev->vcn.num_enc_rings; ++j) {  in vcn_v3_0_hw_init()
366 				ring = &adev->vcn.inst[i].ring_enc[j];  in vcn_v3_0_hw_init()
394 	cancel_delayed_work_sync(&adev->vcn.idle_work);  in vcn_v3_0_hw_fini()
396 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_hw_fini()
397 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_hw_fini()
402 					(adev->vcn.cur_state != AMD_PG_STATE_GATE &&  in vcn_v3_0_hw_fini()
464 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v3_0_mc_resume()
477 			lower_32_bits(adev->vcn.inst[inst].gpu_addr));  in vcn_v3_0_mc_resume()
479 			upper_32_bits(adev->vcn.inst[inst].gpu_addr));  in vcn_v3_0_mc_resume()
488 		lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));  in vcn_v3_0_mc_resume()
490 		upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));  in vcn_v3_0_mc_resume()
496 		lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v3_0_mc_resume()
498 		upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v3_0_mc_resume()
504 		lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));  in vcn_v3_0_mc_resume()
506 		upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));  in vcn_v3_0_mc_resume()
514 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v3_0_mc_resume_dpg_mode()
540 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
543 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
561 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
564 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
581 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
584 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
593 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
596 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
958 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;  in vcn_v3_0_start_dpg_mode()
972 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad…  in vcn_v3_0_start_dpg_mode()
1054 		psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,  in vcn_v3_0_start_dpg_mode()
1055 			(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -  in vcn_v3_0_start_dpg_mode()
1056 				(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));  in vcn_v3_0_start_dpg_mode()
1058 	ring = &adev->vcn.inst[inst_idx].ring_dec;  in vcn_v3_0_start_dpg_mode()
1120 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_start()
1121 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_start()
1125 			r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);  in vcn_v3_0_start()
1245 		ring = &adev->vcn.inst[i].ring_dec;  in vcn_v3_0_start()
1255 		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;  in vcn_v3_0_start()
1276 			ring = &adev->vcn.inst[i].ring_enc[0];  in vcn_v3_0_start()
1285 			ring = &adev->vcn.inst[i].ring_enc[1];  in vcn_v3_0_start()
1339 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v3_0_start_sriov()
1340 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_start_sriov()
1349 		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v3_0_start_sriov()
1366 				lower_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v3_0_start_sriov()
1369 				upper_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v3_0_start_sriov()
1380 		cache_addr = adev->vcn.inst[i].gpu_addr + offset;  in vcn_v3_0_start_sriov()
1394 		cache_addr = adev->vcn.inst[i].gpu_addr + offset +  in vcn_v3_0_start_sriov()
1409 		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {  in vcn_v3_0_start_sriov()
1410 			ring = &adev->vcn.inst[i].ring_enc[j];  in vcn_v3_0_start_sriov()
1424 		ring = &adev->vcn.inst[i].ring_dec;  in vcn_v3_0_start_sriov()
1542 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_stop()
1543 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_stop()
1621 	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {  in vcn_v3_0_pause_dpg_mode()
1623 			adev->vcn.inst[inst_idx].pause_state.fw_based,	new_state->fw_based);  in vcn_v3_0_pause_dpg_mode()
1648 					fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;  in vcn_v3_0_pause_dpg_mode()
1650 					ring = &adev->vcn.inst[inst_idx].ring_enc[0];  in vcn_v3_0_pause_dpg_mode()
1660 					ring = &adev->vcn.inst[inst_idx].ring_enc[1];  in vcn_v3_0_pause_dpg_mode()
1686 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;  in vcn_v3_0_pause_dpg_mode()
1737 		fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr;  in vcn_v3_0_dec_ring_set_wptr()
1955 		if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {  in vcn_v3_0_ring_patch_cs_in_place()
1957 		} else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {  in vcn_v3_0_ring_patch_cs_in_place()
1959 		} else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&  in vcn_v3_0_ring_patch_cs_in_place()
2011 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])  in vcn_v3_0_enc_ring_get_rptr()
2028 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {  in vcn_v3_0_enc_ring_get_wptr()
2052 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {  in vcn_v3_0_enc_ring_set_wptr()
2103 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_set_dec_ring_funcs()
2104 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_set_dec_ring_funcs()
2108 			adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;  in vcn_v3_0_set_dec_ring_funcs()
2110 			adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;  in vcn_v3_0_set_dec_ring_funcs()
2111 		adev->vcn.inst[i].ring_dec.me = i;  in vcn_v3_0_set_dec_ring_funcs()
2121 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_set_enc_ring_funcs()
2122 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_set_enc_ring_funcs()
2125 		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {  in vcn_v3_0_set_enc_ring_funcs()
2126 			adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;  in vcn_v3_0_set_enc_ring_funcs()
2127 			adev->vcn.inst[i].ring_enc[j].me = i;  in vcn_v3_0_set_enc_ring_funcs()
2129 		if (adev->vcn.num_enc_rings > 0)  in vcn_v3_0_set_enc_ring_funcs()
2139 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_is_idle()
2140 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_is_idle()
2154 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_wait_for_idle()
2155 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_wait_for_idle()
2174 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_set_clockgating_state()
2175 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_set_clockgating_state()
2201 		adev->vcn.cur_state = AMD_PG_STATE_UNGATE;  in vcn_v3_0_set_powergating_state()
2205 	if(state == adev->vcn.cur_state)  in vcn_v3_0_set_powergating_state()
2214 		adev->vcn.cur_state = state;  in vcn_v3_0_set_powergating_state()
2249 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);  in vcn_v3_0_process_interrupt()
2252 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);  in vcn_v3_0_process_interrupt()
2255 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);  in vcn_v3_0_process_interrupt()
2275 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v3_0_set_irq_funcs()
2276 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v3_0_set_irq_funcs()
2279 		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;  in vcn_v3_0_set_irq_funcs()
2280 		adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;  in vcn_v3_0_set_irq_funcs()