512 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v3_0_mc_resume_dpg_mode()  argument
519 		if (!indirect) {  in vcn_v3_0_mc_resume_dpg_mode()
522 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
525 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
527 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
530 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
532 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
534 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
540 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
543 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
547 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
550 	if (!indirect)  in vcn_v3_0_mc_resume_dpg_mode()
552 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
555 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
558 	if (!indirect) {  in vcn_v3_0_mc_resume_dpg_mode()
561 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
564 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
566 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
569 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
571 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
573 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
576 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
581 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
584 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
586 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
588 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
593 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
596 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
598 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
601 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
605 		UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
841 		uint8_t sram_sel, int inst_idx, uint8_t indirect)  in vcn_v3_0_clock_gating_dpg_mode()  argument
873 		VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
877 		VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
881 		VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
885 		VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
956 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v3_0_start_dpg_mode()  argument
971 	if (indirect)  in vcn_v3_0_start_dpg_mode()
975 	vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);  in vcn_v3_0_start_dpg_mode()
982 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
986 		VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
998 		VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1002 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1009 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1016 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1022 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1024 	vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);  in vcn_v3_0_start_dpg_mode()
1027 		VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1029 		VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1033 		VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1037 		VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1042 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1047 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1051 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1053 	if (indirect)  in vcn_v3_0_start_dpg_mode()