103 				harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);  in vcn_v3_0_early_init()
194 		adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);  in vcn_v3_0_sw_init()
196 		adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v3_0_sw_init()
198 		adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v3_0_sw_init()
200 		adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);  in vcn_v3_0_sw_init()
202 		adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);  in vcn_v3_0_sw_init()
403 					 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {  in vcn_v3_0_hw_fini()
469 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
471 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
473 		WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);  in vcn_v3_0_mc_resume()
476 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
478 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
481 		WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,  in vcn_v3_0_mc_resume()
484 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);  in vcn_v3_0_mc_resume()
487 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
489 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
491 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);  in vcn_v3_0_mc_resume()
492 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);  in vcn_v3_0_mc_resume()
495 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
497 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
499 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);  in vcn_v3_0_mc_resume()
500 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);  in vcn_v3_0_mc_resume()
503 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
505 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
507 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);  in vcn_v3_0_mc_resume()
508 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,  in vcn_v3_0_mc_resume()
521 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
524 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
527 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
530 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
532 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
534 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
539 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
542 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
546 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),  in vcn_v3_0_mc_resume_dpg_mode()
552 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
555 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
560 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
563 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
566 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
569 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
571 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
573 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
576 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
580 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
583 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
586 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
588 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
592 			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
595 			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
598 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
600 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),  in vcn_v3_0_mc_resume_dpg_mode()
628 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_disable_static_power_gating()
629 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,  in vcn_v3_0_disable_static_power_gating()
646 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_disable_static_power_gating()
647 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0,  0x3F3FFFFF);  in vcn_v3_0_disable_static_power_gating()
650 	data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);  in vcn_v3_0_disable_static_power_gating()
656 	WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);  in vcn_v3_0_disable_static_power_gating()
665 		data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);  in vcn_v3_0_enable_static_power_gating()
668 		WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);  in vcn_v3_0_enable_static_power_gating()
684 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_enable_static_power_gating()
700 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);  in vcn_v3_0_enable_static_power_gating()
717 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
724 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
726 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);  in vcn_v3_0_disable_clock_gating()
748 	WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);  in vcn_v3_0_disable_clock_gating()
750 	SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);  in vcn_v3_0_disable_clock_gating()
752 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
773 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
775 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);  in vcn_v3_0_disable_clock_gating()
807 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);  in vcn_v3_0_disable_clock_gating()
809 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);  in vcn_v3_0_disable_clock_gating()
815 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);  in vcn_v3_0_disable_clock_gating()
817 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
837 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
873 		VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
877 		VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
881 		VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
885 		VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
901 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
908 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
910 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
931 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
933 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
953 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
963 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,  in vcn_v3_0_start_dpg_mode()
966 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);  in vcn_v3_0_start_dpg_mode()
969 	WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);  in vcn_v3_0_start_dpg_mode()
982 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
986 		VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
998 		VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1001 		VCN, inst_idx, mmUVD_MPC_CNTL),  in vcn_v3_0_start_dpg_mode()
1005 		VCN, inst_idx, mmUVD_MPC_SET_MUXA0),  in vcn_v3_0_start_dpg_mode()
1012 		VCN, inst_idx, mmUVD_MPC_SET_MUXB0),  in vcn_v3_0_start_dpg_mode()
1019 		VCN, inst_idx, mmUVD_MPC_SET_MUX),  in vcn_v3_0_start_dpg_mode()
1027 		VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1029 		VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1033 		VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1037 		VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1042 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1046 		VCN, inst_idx, mmUVD_MASTINT_EN),  in vcn_v3_0_start_dpg_mode()
1051 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1066 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v3_0_start_dpg_mode()
1069 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_start_dpg_mode()
1075 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);  in vcn_v3_0_start_dpg_mode()
1078 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,  in vcn_v3_0_start_dpg_mode()
1082 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v3_0_start_dpg_mode()
1084 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v3_0_start_dpg_mode()
1088 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);  in vcn_v3_0_start_dpg_mode()
1090 	WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);  in vcn_v3_0_start_dpg_mode()
1092 	ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_start_dpg_mode()
1093 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,  in vcn_v3_0_start_dpg_mode()
1104 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_start_dpg_mode()
1133 		tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;  in vcn_v3_0_start()
1134 		WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);  in vcn_v3_0_start()
1140 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_start()
1144 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,  in vcn_v3_0_start()
1148 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,  in vcn_v3_0_start()
1151 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_start()
1154 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_start()
1157 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);  in vcn_v3_0_start()
1158 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |  in vcn_v3_0_start()
1165 		tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);  in vcn_v3_0_start()
1168 		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);  in vcn_v3_0_start()
1171 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,  in vcn_v3_0_start()
1178 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,  in vcn_v3_0_start()
1185 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,  in vcn_v3_0_start()
1193 		WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,  in vcn_v3_0_start()
1197 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,  in vcn_v3_0_start()
1201 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_start()
1208 				status = RREG32_SOC15(VCN, i, mmUVD_STATUS);  in vcn_v3_0_start()
1218 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_start()
1222 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_start()
1235 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),  in vcn_v3_0_start()
1240 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,  in vcn_v3_0_start()
1243 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);  in vcn_v3_0_start()
1253 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v3_0_start()
1259 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v3_0_start()
1261 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v3_0_start()
1265 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);  in vcn_v3_0_start()
1267 		WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);  in vcn_v3_0_start()
1268 		ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_start()
1269 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,  in vcn_v3_0_start()
1277 			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1278 			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1279 			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v3_0_start()
1280 			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_start()
1281 			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v3_0_start()
1286 			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1287 			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1288 			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v3_0_start()
1289 			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_start()
1290 			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v3_0_start()
1345 		MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1353 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1356 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1360 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1364 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1367 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1371 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1376 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1381 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1384 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1387 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1390 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1396 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1399 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1402 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1405 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1413 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1416 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1419 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1427 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1430 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1440 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1464 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));  in vcn_v3_0_start_sriov()
1465 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));  in vcn_v3_0_start_sriov()
1468 	tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);  in vcn_v3_0_start_sriov()
1472 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);  in vcn_v3_0_start_sriov()
1476 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);  in vcn_v3_0_start_sriov()
1479 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);  in vcn_v3_0_start_sriov()
1485 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);  in vcn_v3_0_start_sriov()
1491 		resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);  in vcn_v3_0_start_sriov()
1514 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v3_0_stop_dpg_mode()
1518 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);  in vcn_v3_0_stop_dpg_mode()
1519 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1521 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);  in vcn_v3_0_stop_dpg_mode()
1522 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1524 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;  in vcn_v3_0_stop_dpg_mode()
1525 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1527 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v3_0_stop_dpg_mode()
1531 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,  in vcn_v3_0_stop_dpg_mode()
1552 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);  in vcn_v3_0_stop()
1560 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v3_0_stop()
1565 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);  in vcn_v3_0_stop()
1567 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);  in vcn_v3_0_stop()
1570 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v3_0_stop()
1575 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),  in vcn_v3_0_stop()
1580 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_stop()
1585 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_stop()
1589 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_stop()
1591 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_stop()
1592 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_stop()
1594 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_stop()
1597 		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);  in vcn_v3_0_stop()
1624 		reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &  in vcn_v3_0_pause_dpg_mode()
1628 			ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,  in vcn_v3_0_pause_dpg_mode()
1634 				WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v3_0_pause_dpg_mode()
1637 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,  in vcn_v3_0_pause_dpg_mode()
1642 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_pause_dpg_mode()
1652 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v3_0_pause_dpg_mode()
1653 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_pause_dpg_mode()
1654 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v3_0_pause_dpg_mode()
1655 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1656 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1662 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v3_0_pause_dpg_mode()
1663 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_pause_dpg_mode()
1664 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v3_0_pause_dpg_mode()
1665 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1666 					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1670 					WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);  in vcn_v3_0_pause_dpg_mode()
1671 					WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);  in vcn_v3_0_pause_dpg_mode()
1675 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_pause_dpg_mode()
1678 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,  in vcn_v3_0_pause_dpg_mode()
1684 			WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v3_0_pause_dpg_mode()
1703 	return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_dec_ring_get_rptr()
1720 		return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);  in vcn_v3_0_dec_ring_get_wptr()
1739 		WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,  in vcn_v3_0_dec_ring_set_wptr()
1747 		WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_dec_ring_set_wptr()
2012 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);  in vcn_v3_0_enc_ring_get_rptr()
2014 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);  in vcn_v3_0_enc_ring_get_rptr()
2032 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);  in vcn_v3_0_enc_ring_get_wptr()
2037 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);  in vcn_v3_0_enc_ring_get_wptr()
2057 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_enc_ring_set_wptr()
2064 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_enc_ring_set_wptr()
2143 		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v3_0_is_idle()
2158 		ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v3_0_wait_for_idle()
2179 			if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)  in vcn_v3_0_set_clockgating_state()