443 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v2_5_mc_resume_dpg_mode()  argument
450 		if (!indirect) {  in vcn_v2_5_mc_resume_dpg_mode()
453 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
456 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
458 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
461 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
463 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
465 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
471 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
474 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
478 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
481 	if (!indirect)  in vcn_v2_5_mc_resume_dpg_mode()
483 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
486 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
489 	if (!indirect) {  in vcn_v2_5_mc_resume_dpg_mode()
492 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
495 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
497 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
500 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
502 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
504 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
507 		VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
512 		lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
515 		upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
517 		VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
519 		VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
524 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
527 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
529 		VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
532 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
536 		VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
657 		uint8_t sram_sel, int inst_idx, uint8_t indirect)  in vcn_v2_5_clock_gating_dpg_mode()  argument
689 		VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
693 		VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
697 		VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
701 		VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
766 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v2_5_start_dpg_mode()  argument
781 	if (indirect)  in vcn_v2_5_start_dpg_mode()
785 	vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);  in vcn_v2_5_start_dpg_mode()
792 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
796 		VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
808 		VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
812 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v2_5_start_dpg_mode()
819 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
826 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
832 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
834 	vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);  in vcn_v2_5_start_dpg_mode()
837 		VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v2_5_start_dpg_mode()
839 		VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v2_5_start_dpg_mode()
843 		VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
847 		VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
852 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
857 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v2_5_start_dpg_mode()
859 	if (indirect)  in vcn_v2_5_start_dpg_mode()