238 		 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {  in vcn_v1_0_hw_fini()
445 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
454 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
456 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
458 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
461 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
469 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
471 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
492 	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
494 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
515 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
518 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
543 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
545 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
556 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
571 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
578 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
580 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_enable_clock_gating()
582 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_enable_clock_gating()
585 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
592 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
594 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
615 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
617 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
628 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
702 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
703 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);  in vcn_1_0_disable_static_power_gating()
716 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
717 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);  in vcn_1_0_disable_static_power_gating()
722 	data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_disable_static_power_gating()
727 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_disable_static_power_gating()
736 		data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_enable_static_power_gating()
739 		WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_enable_static_power_gating()
754 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_enable_static_power_gating()
767 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);  in vcn_1_0_enable_static_power_gating()
1337 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v1_0_is_idle()
1345 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v1_0_wait_for_idle()