191 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg()
192 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg()
201 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg()
202 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg()
210 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg64()
211 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg64()
220 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg64()
221 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg64()
328 	return adev->nbio.funcs->get_memsize(adev);  in soc15_get_config_memsize()
531 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);  in soc15_asic_baco_reset()
539 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);  in soc15_asic_baco_reset()
696 	    (adev->nbio.funcs->program_aspm))  in soc15_program_aspm()
697 		adev->nbio.funcs->program_aspm(adev);  in soc15_program_aspm()
703 	adev->nbio.funcs->enable_doorbell_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
704 	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
718 	return adev->nbio.funcs->get_rev_id(adev);  in soc15_get_rev_id()
776 		adev->nbio.funcs = &nbio_v7_0_funcs;  in soc15_set_ip_blocks()
777 		adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;  in soc15_set_ip_blocks()
781 		adev->nbio.funcs = &nbio_v7_4_funcs;  in soc15_set_ip_blocks()
782 		adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;  in soc15_set_ip_blocks()
784 		adev->nbio.funcs = &nbio_v6_1_funcs;  in soc15_set_ip_blocks()
785 		adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;  in soc15_set_ip_blocks()
1386 	if (adev->nbio.ras_funcs &&  in soc15_common_late_init()
1387 	    adev->nbio.ras_funcs->ras_late_init)  in soc15_common_late_init()
1388 		r = adev->nbio.ras_funcs->ras_late_init(adev);  in soc15_common_late_init()
1409 	if (adev->nbio.ras_funcs &&  in soc15_common_sw_fini()
1410 	    adev->nbio.ras_funcs->ras_fini)  in soc15_common_sw_fini()
1411 		adev->nbio.ras_funcs->ras_fini(adev);  in soc15_common_sw_fini()
1425 			adev->nbio.funcs->sdma_doorbell_range(adev, i,  in soc15_doorbell_range_init()
1430 		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,  in soc15_doorbell_range_init()
1444 	adev->nbio.funcs->init_registers(adev);  in soc15_common_hw_init()
1449 	if (adev->nbio.funcs->remap_hdp_registers)  in soc15_common_hw_init()
1450 		adev->nbio.funcs->remap_hdp_registers(adev);  in soc15_common_hw_init()
1473 	if (adev->nbio.ras_if &&  in soc15_common_hw_fini()
1474 	    amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {  in soc15_common_hw_fini()
1475 		if (adev->nbio.ras_funcs &&  in soc15_common_hw_fini()
1476 		    adev->nbio.ras_funcs->init_ras_controller_interrupt)  in soc15_common_hw_fini()
1477 			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);  in soc15_common_hw_fini()
1478 		if (adev->nbio.ras_funcs &&  in soc15_common_hw_fini()
1479 		    adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)  in soc15_common_hw_fini()
1480 			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);  in soc15_common_hw_fini()
1571 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1573 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1588 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1590 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1618 	adev->nbio.funcs->get_clockgating_state(adev, flags);  in soc15_common_get_clockgating_state()