Lines Matching full:sdma
111 release_firmware(adev->sdma.instance[0].fw); in sdma_v5_2_destroy_inst_ctx()
113 memset((void *)adev->sdma.instance, 0, in sdma_v5_2_destroy_inst_ctx()
164 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); in sdma_v5_2_init_microcode()
168 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); in sdma_v5_2_init_microcode()
172 for (i = 1; i < adev->sdma.num_instances; i++) in sdma_v5_2_init_microcode()
173 memcpy((void *)&adev->sdma.instance[i], in sdma_v5_2_init_microcode()
174 (void *)&adev->sdma.instance[0], in sdma_v5_2_init_microcode()
184 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_init_microcode()
187 info->fw = adev->sdma.instance[i].fw; in sdma_v5_2_init_microcode()
318 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_insert_nop() local
322 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_insert_nop()
474 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; in sdma_v5_2_gfx_stop()
475 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; in sdma_v5_2_gfx_stop()
476 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; in sdma_v5_2_gfx_stop()
477 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; in sdma_v5_2_gfx_stop()
487 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_stop()
546 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
581 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
609 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
610 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume()
766 * sdma_v5_2_load_microcode - load the sDMA ME ucode
783 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
784 if (!adev->sdma.instance[i].fw) in sdma_v5_2_load_microcode()
787 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_2_load_microcode()
792 (adev->sdma.instance[i].fw->data + in sdma_v5_2_load_microcode()
803 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); in sdma_v5_2_load_microcode()
816 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_soft_reset()
880 /* enable sdma ring preemption */ in sdma_v5_2_start()
1037 * Update PTEs by copying them from the GART using sDMA.
1065 * Update PTEs by writing them manually using sDMA.
1086 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1095 * Update the page tables using sDMA.
1125 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_pad_ib() local
1131 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_pad_ib()
1168 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1175 * using sDMA.
1222 adev->sdma.num_instances = 4; in sdma_v5_2_early_init()
1226 adev->sdma.num_instances = 2; in sdma_v5_2_early_init()
1231 adev->sdma.num_instances = 1; in sdma_v5_2_early_init()
1285 /* SDMA trap event */ in sdma_v5_2_sw_init()
1286 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1289 &adev->sdma.trap_irq); in sdma_v5_2_sw_init()
1296 DRM_ERROR("Failed to load sdma firmware!\n"); in sdma_v5_2_sw_init()
1300 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1301 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_sw_init()
1312 sprintf(ring->name, "sdma%d", i); in sdma_v5_2_sw_init()
1313 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v5_2_sw_init()
1328 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_2_sw_fini()
1329 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v5_2_sw_fini()
1378 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_is_idle()
1473 DRM_DEBUG("IH: SDMA trap\n"); in sdma_v5_2_process_trap_irq()
1478 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_2_process_trap_irq()
1494 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v5_2_process_trap_irq()
1510 amdgpu_fence_process(&adev->sdma.instance[2].ring); in sdma_v5_2_process_trap_irq()
1526 amdgpu_fence_process(&adev->sdma.instance[3].ring); in sdma_v5_2_process_trap_irq()
1556 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_update_medium_grain_clock_gating()
1558 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) in sdma_v5_2_update_medium_grain_clock_gating()
1562 /* Enable sdma clock gating */ in sdma_v5_2_update_medium_grain_clock_gating()
1573 /* Disable sdma clock gating */ in sdma_v5_2_update_medium_grain_clock_gating()
1593 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_update_medium_grain_light_sleep()
1595 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) in sdma_v5_2_update_medium_grain_light_sleep()
1599 /* Enable sdma mem light sleep */ in sdma_v5_2_update_medium_grain_light_sleep()
1606 /* Disable sdma mem light sleep */ in sdma_v5_2_update_medium_grain_light_sleep()
1722 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_set_ring_funcs()
1723 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; in sdma_v5_2_set_ring_funcs()
1724 adev->sdma.instance[i].ring.me = i; in sdma_v5_2_set_ring_funcs()
1739 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_2_set_irq_funcs()
1740 adev->sdma.num_instances; in sdma_v5_2_set_irq_funcs()
1741 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; in sdma_v5_2_set_irq_funcs()
1742 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; in sdma_v5_2_set_irq_funcs()
1746 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1776 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1811 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_2_set_buffer_funcs()
1828 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_set_vm_pte_funcs()
1830 &adev->sdma.instance[i].ring.sched; in sdma_v5_2_set_vm_pte_funcs()
1832 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_2_set_vm_pte_funcs()