428 				   struct amdgpu_ib *ib,  in sdma_v3_0_ring_emit_ib()  argument
439 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);  in sdma_v3_0_ring_emit_ib()
440 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in sdma_v3_0_ring_emit_ib()
441 	amdgpu_ring_write(ring, ib->length_dw);  in sdma_v3_0_ring_emit_ib()
877 	struct amdgpu_ib ib;  in sdma_v3_0_ring_test_ib()  local
891 	memset(&ib, 0, sizeof(ib));  in sdma_v3_0_ring_test_ib()
893 					AMDGPU_IB_POOL_DIRECT, &ib);  in sdma_v3_0_ring_test_ib()
897 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v3_0_ring_test_ib()
899 	ib.ptr[1] = lower_32_bits(gpu_addr);  in sdma_v3_0_ring_test_ib()
900 	ib.ptr[2] = upper_32_bits(gpu_addr);  in sdma_v3_0_ring_test_ib()
901 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);  in sdma_v3_0_ring_test_ib()
902 	ib.ptr[4] = 0xDEADBEEF;  in sdma_v3_0_ring_test_ib()
903 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v3_0_ring_test_ib()
904 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v3_0_ring_test_ib()
905 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v3_0_ring_test_ib()
906 	ib.length_dw = 8;  in sdma_v3_0_ring_test_ib()
908 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);  in sdma_v3_0_ring_test_ib()
925 	amdgpu_ib_free(adev, &ib, NULL);  in sdma_v3_0_ring_test_ib()
942 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,  in sdma_v3_0_vm_copy_pte()  argument
948 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v3_0_vm_copy_pte()
950 	ib->ptr[ib->length_dw++] = bytes;  in sdma_v3_0_vm_copy_pte()
951 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v3_0_vm_copy_pte()
952 	ib->ptr[ib->length_dw++] = lower_32_bits(src);  in sdma_v3_0_vm_copy_pte()
953 	ib->ptr[ib->length_dw++] = upper_32_bits(src);  in sdma_v3_0_vm_copy_pte()
954 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v3_0_vm_copy_pte()
955 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v3_0_vm_copy_pte()
969 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,  in sdma_v3_0_vm_write_pte()  argument
975 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v3_0_vm_write_pte()
977 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v3_0_vm_write_pte()
978 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v3_0_vm_write_pte()
979 	ib->ptr[ib->length_dw++] = ndw;  in sdma_v3_0_vm_write_pte()
981 		ib->ptr[ib->length_dw++] = lower_32_bits(value);  in sdma_v3_0_vm_write_pte()
982 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in sdma_v3_0_vm_write_pte()
999 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,  in sdma_v3_0_vm_set_pte_pde()  argument
1004 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);  in sdma_v3_0_vm_set_pte_pde()
1005 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */  in sdma_v3_0_vm_set_pte_pde()
1006 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v3_0_vm_set_pte_pde()
1007 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */  in sdma_v3_0_vm_set_pte_pde()
1008 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);  in sdma_v3_0_vm_set_pte_pde()
1009 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */  in sdma_v3_0_vm_set_pte_pde()
1010 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);  in sdma_v3_0_vm_set_pte_pde()
1011 	ib->ptr[ib->length_dw++] = incr; /* increment size */  in sdma_v3_0_vm_set_pte_pde()
1012 	ib->ptr[ib->length_dw++] = 0;  in sdma_v3_0_vm_set_pte_pde()
1013 	ib->ptr[ib->length_dw++] = count; /* number of entries */  in sdma_v3_0_vm_set_pte_pde()
1023 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)  in sdma_v3_0_ring_pad_ib()  argument
1029 	pad_count = (-ib->length_dw) & 7;  in sdma_v3_0_ring_pad_ib()
1032 			ib->ptr[ib->length_dw++] =  in sdma_v3_0_ring_pad_ib()
1036 			ib->ptr[ib->length_dw++] =  in sdma_v3_0_ring_pad_ib()
1644 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,  in sdma_v3_0_emit_copy_buffer()  argument
1650 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v3_0_emit_copy_buffer()
1652 	ib->ptr[ib->length_dw++] = byte_count;  in sdma_v3_0_emit_copy_buffer()
1653 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v3_0_emit_copy_buffer()
1654 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);  in sdma_v3_0_emit_copy_buffer()
1655 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);  in sdma_v3_0_emit_copy_buffer()
1656 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v3_0_emit_copy_buffer()
1657 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v3_0_emit_copy_buffer()
1670 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,  in sdma_v3_0_emit_fill_buffer()  argument
1675 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);  in sdma_v3_0_emit_fill_buffer()
1676 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v3_0_emit_fill_buffer()
1677 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v3_0_emit_fill_buffer()
1678 	ib->ptr[ib->length_dw++] = src_data;  in sdma_v3_0_emit_fill_buffer()
1679 	ib->ptr[ib->length_dw++] = byte_count;  in sdma_v3_0_emit_fill_buffer()