Lines Matching +full:64 +full:kb

124 …ddr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
127 …f_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
129 …_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
150 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
152 …f_size;              /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
160 #define GFX_BUF_MAX_DESC        64
165 …e;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
184 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
186     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
195 …y_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
268 …  fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
279 …; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
294 …_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
361     union psp_gfx_uresp uresp;      /* +64 response union containing command-specific responses */
377 …f_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
402 …f_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
414                 /* total 64 bytes */