Lines Matching refs:adev
180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
183 switch (adev->asic_type) { in nv_query_video_codecs()
185 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
233 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
236 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
237 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
239 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
242 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
246 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
247 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
249 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
252 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
255 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
256 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
258 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in nv_pcie_rreg64()
261 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_port_rreg() argument
265 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in nv_pcie_port_rreg()
266 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); in nv_pcie_port_rreg()
268 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_port_rreg()
272 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_port_rreg()
276 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in nv_pcie_wreg64() argument
280 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
281 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
283 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in nv_pcie_wreg64()
286 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_port_wreg() argument
290 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in nv_pcie_port_wreg()
291 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); in nv_pcie_port_wreg()
293 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_port_wreg()
298 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_port_wreg()
301 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
309 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
312 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
316 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
323 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
326 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
329 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
331 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
334 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
336 return adev->clock.spll.reference_freq; in nv_get_xclk()
340 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
352 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
357 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
363 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, in nv_read_bios_from_rom() argument
375 if (adev->flags & AMD_IS_APU) in nv_read_bios_from_rom()
382 adev->smuio.funcs->get_rom_index_offset(adev); in nv_read_bios_from_rom()
384 adev->smuio.funcs->get_rom_data_offset(adev); in nv_read_bios_from_rom()
417 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
422 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
424 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
429 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
430 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
434 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
439 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
442 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
447 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
456 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ in nv_read_register()
458 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) in nv_read_register()
461 *value = nv_get_register_value(adev, in nv_read_register()
469 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
474 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
477 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
479 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
481 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
483 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
485 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
488 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
489 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
496 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
502 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
511 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
514 switch (adev->asic_type) { in nv_asic_reset_method()
524 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
531 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
535 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
537 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
538 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
541 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
542 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
545 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
546 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
549 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
550 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
557 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
563 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
569 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
571 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
577 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
584 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
589 if (!(adev->flags & AMD_IS_APU) && in nv_program_aspm()
590 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
591 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
595 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
598 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
599 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
621 static int nv_reg_base_init(struct amdgpu_device *adev) in nv_reg_base_init() argument
626 r = amdgpu_discovery_reg_base_init(adev); in nv_reg_base_init()
633 amdgpu_discovery_harvest_ip(adev); in nv_reg_base_init()
634 if (nv_is_headless_sku(adev->pdev)) { in nv_reg_base_init()
635 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; in nv_reg_base_init()
636 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; in nv_reg_base_init()
643 switch (adev->asic_type) { in nv_reg_base_init()
645 navi10_reg_base_init(adev); in nv_reg_base_init()
648 navi14_reg_base_init(adev); in nv_reg_base_init()
651 navi12_reg_base_init(adev); in nv_reg_base_init()
655 sienna_cichlid_reg_base_init(adev); in nv_reg_base_init()
658 vangogh_reg_base_init(adev); in nv_reg_base_init()
661 dimgrey_cavefish_reg_base_init(adev); in nv_reg_base_init()
664 beige_goby_reg_base_init(adev); in nv_reg_base_init()
667 yellow_carp_reg_base_init(adev); in nv_reg_base_init()
670 cyan_skillfish_reg_base_init(adev); in nv_reg_base_init()
679 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
681 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
684 int nv_set_ip_blocks(struct amdgpu_device *adev) in nv_set_ip_blocks() argument
688 if (adev->asic_type == CHIP_CYAN_SKILLFISH) { in nv_set_ip_blocks()
689 adev->nbio.funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
690 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in nv_set_ip_blocks()
691 } else if (adev->flags & AMD_IS_APU) { in nv_set_ip_blocks()
692 adev->nbio.funcs = &nbio_v7_2_funcs; in nv_set_ip_blocks()
693 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; in nv_set_ip_blocks()
695 adev->nbio.funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
696 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in nv_set_ip_blocks()
698 adev->hdp.funcs = &hdp_v5_0_funcs; in nv_set_ip_blocks()
700 if (adev->asic_type >= CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
701 adev->smuio.funcs = &smuio_v11_0_6_funcs; in nv_set_ip_blocks()
703 adev->smuio.funcs = &smuio_v11_0_funcs; in nv_set_ip_blocks()
705 if (adev->asic_type == CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
706 adev->gmc.xgmi.supported = true; in nv_set_ip_blocks()
709 r = nv_reg_base_init(adev); in nv_set_ip_blocks()
713 switch (adev->asic_type) { in nv_set_ip_blocks()
716 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
717 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
718 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
719 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
720 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
721 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
722 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
723 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
724 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
726 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
727 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
729 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
730 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
731 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
732 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
733 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
734 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
735 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
736 if (adev->enable_mes) in nv_set_ip_blocks()
737 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
740 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
741 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
742 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
743 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
744 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
746 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
747 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
749 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) in nv_set_ip_blocks()
750 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
751 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
752 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
754 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
755 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
757 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
758 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
759 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
760 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
761 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
762 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
763 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
764 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
767 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
768 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
769 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
770 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
771 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
772 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
774 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
775 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
776 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
778 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
779 is_support_sw_smu(adev)) in nv_set_ip_blocks()
780 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
781 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
782 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
784 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
785 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
787 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
788 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
789 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
790 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
791 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
792 if (adev->enable_mes) in nv_set_ip_blocks()
793 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
796 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
797 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
798 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
799 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
800 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
801 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
802 is_support_sw_smu(adev)) in nv_set_ip_blocks()
803 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
804 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
805 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
807 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
808 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
810 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
811 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
812 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
813 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
814 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
815 is_support_sw_smu(adev)) in nv_set_ip_blocks()
816 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
819 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
820 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
821 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
822 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
823 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
824 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
825 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
826 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
828 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
829 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
831 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
832 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
833 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
834 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
837 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
838 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
839 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
840 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
841 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
842 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
843 is_support_sw_smu(adev)) in nv_set_ip_blocks()
844 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
845 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
846 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
848 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
849 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
851 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
852 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
853 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
854 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
857 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
858 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
859 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
860 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
861 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
862 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
863 is_support_sw_smu(adev)) in nv_set_ip_blocks()
864 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
865 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
866 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
867 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
868 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
870 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
871 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
873 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
874 is_support_sw_smu(adev)) in nv_set_ip_blocks()
875 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
876 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
879 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
880 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
881 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
882 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
883 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); in nv_set_ip_blocks()
884 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); in nv_set_ip_blocks()
885 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
886 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
887 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
888 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
889 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
890 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
892 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
893 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
895 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
896 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
899 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
900 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
901 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
902 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { in nv_set_ip_blocks()
903 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
904 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); in nv_set_ip_blocks()
905 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
907 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
908 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
909 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
910 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
919 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
921 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
924 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
929 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
933 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
946 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) in nv_get_pcie_replay_count() argument
956 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
958 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
959 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
960 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
961 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
962 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
963 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
964 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
965 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
966 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
967 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
968 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
969 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
970 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
971 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; in nv_init_doorbell_index()
972 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
973 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
974 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
975 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
976 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
977 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
978 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
979 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
980 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
981 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
982 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
984 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
985 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
988 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
992 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
996 amdgpu_gfx_rlc_enter_safe_mode(adev); in nv_update_umd_stable_pstate()
998 amdgpu_gfx_rlc_exit_safe_mode(adev); in nv_update_umd_stable_pstate()
1000 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
1001 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
1003 if (!(adev->flags & AMD_IS_APU) && in nv_update_umd_stable_pstate()
1004 (adev->nbio.funcs->enable_aspm)) in nv_update_umd_stable_pstate()
1005 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
1035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
1037 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
1038 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
1039 adev->smc_rreg = NULL; in nv_common_early_init()
1040 adev->smc_wreg = NULL; in nv_common_early_init()
1041 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
1042 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
1043 adev->pcie_rreg64 = &nv_pcie_rreg64; in nv_common_early_init()
1044 adev->pcie_wreg64 = &nv_pcie_wreg64; in nv_common_early_init()
1045 adev->pciep_rreg = &nv_pcie_port_rreg; in nv_common_early_init()
1046 adev->pciep_wreg = &nv_pcie_port_wreg; in nv_common_early_init()
1049 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
1050 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
1052 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
1053 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
1055 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
1057 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
1058 adev->external_rev_id = 0xff; in nv_common_early_init()
1059 switch (adev->asic_type) { in nv_common_early_init()
1061 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1076 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1080 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
1083 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1098 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1101 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
1104 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1120 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1128 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
1129 adev->rev_id = 0; in nv_common_early_init()
1130 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
1133 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1144 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1149 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1151 adev->cg_flags = 0; in nv_common_early_init()
1152 adev->pg_flags = 0; in nv_common_early_init()
1154 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
1157 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1168 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1173 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
1177 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1192 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
1196 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
1197 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
1200 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1211 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1216 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
1219 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1229 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1233 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
1236 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1255 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
1259 if (adev->pdev->device == 0x1681) in nv_common_early_init()
1260 adev->external_rev_id = 0x20; in nv_common_early_init()
1262 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
1265 adev->cg_flags = 0; in nv_common_early_init()
1266 adev->pg_flags = 0; in nv_common_early_init()
1267 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
1274 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
1275 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1279 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1280 amdgpu_virt_init_setting(adev); in nv_common_early_init()
1281 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
1291 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1292 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
1293 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
1303 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
1305 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1306 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
1320 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1321 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1323 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
1324 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
1327 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
1329 nv_program_aspm(adev); in nv_common_hw_init()
1331 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1336 if (adev->nbio.funcs->remap_hdp_registers) in nv_common_hw_init()
1337 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1339 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
1349 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
1358 return nv_common_hw_fini(adev); in nv_common_suspend()
1363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
1365 return nv_common_hw_init(adev); in nv_common_resume()
1386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1388 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1391 switch (adev->asic_type) { in nv_common_set_clockgating_state()
1399 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1401 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1403 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1405 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1425 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1428 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1430 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1432 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()