463 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_insert_start()
467 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_insert_start()
481 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_insert_end()
485 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_insert_end()
505 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
509 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
513 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
517 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
521 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
525 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
529 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
533 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_fence()
537 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));  in jpeg_v2_0_dec_ring_emit_fence()
558 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
562 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
566 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
570 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
574 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
578 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
582 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
586 	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));  in jpeg_v2_0_dec_ring_emit_ib()
589 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
593 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
597 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
607 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
611 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
615 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
620 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));  in jpeg_v2_0_dec_ring_emit_reg_wait()
623 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_reg_wait()
648 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_wreg()
653 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));  in jpeg_v2_0_dec_ring_emit_wreg()
656 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_wreg()
669 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));  in jpeg_v2_0_dec_ring_nop()