Lines Matching full:ring
65 * Set ring and irq function pointers
89 struct amdgpu_ring *ring; in jpeg_v2_0_sw_init() local
106 ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
107 ring->use_doorbell = true; in jpeg_v2_0_sw_init()
108 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in jpeg_v2_0_sw_init()
109 sprintf(ring->name, "jpeg_dec"); in jpeg_v2_0_sw_init()
110 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
151 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init() local
154 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v2_0_hw_init()
157 r = amdgpu_ring_test_helper(ring); in jpeg_v2_0_hw_init()
169 * Stop the JPEG block, mark ring as not ready any more
334 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_start() local
362 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
364 upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
368 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
369 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
407 * @ring: amdgpu_ring pointer
411 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_rptr() argument
413 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_rptr()
421 * @ring: amdgpu_ring pointer
425 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_wptr() argument
427 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_wptr()
429 if (ring->use_doorbell) in jpeg_v2_0_dec_ring_get_wptr()
430 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
438 * @ring: amdgpu_ring pointer
442 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_set_wptr() argument
444 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_set_wptr()
446 if (ring->use_doorbell) { in jpeg_v2_0_dec_ring_set_wptr()
447 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
448 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
450 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
457 * @ring: amdgpu_ring pointer
459 * Write a start command to the ring.
461 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_start() argument
463 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
465 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
467 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
469 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
475 * @ring: amdgpu_ring pointer
477 * Write a end command to the ring.
479 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_end() argument
481 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
483 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
485 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
493 * @ring: amdgpu_ring pointer
498 * Write a fence and a trap command to the ring.
500 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in jpeg_v2_0_dec_ring_emit_fence() argument
505 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
507 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
511 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
513 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
515 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
517 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
519 amdgpu_ring_write(ring, upper_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
521 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
523 amdgpu_ring_write(ring, 0x8); in jpeg_v2_0_dec_ring_emit_fence()
525 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
527 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
529 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
531 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v2_0_dec_ring_emit_fence()
533 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_fence()
535 amdgpu_ring_write(ring, 0x1); in jpeg_v2_0_dec_ring_emit_fence()
537 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
538 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
544 * @ring: amdgpu_ring pointer
549 * Write ring commands to execute the indirect buffer.
551 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_ib() argument
558 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
560 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in jpeg_v2_0_dec_ring_emit_ib()
562 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
564 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in jpeg_v2_0_dec_ring_emit_ib()
566 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
568 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
570 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
572 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
574 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
576 amdgpu_ring_write(ring, ib->length_dw); in jpeg_v2_0_dec_ring_emit_ib()
578 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
580 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
582 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
584 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
586 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v2_0_dec_ring_emit_ib()
587 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
589 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
591 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_ib()
593 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
595 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
597 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
599 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
602 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in jpeg_v2_0_dec_ring_emit_reg_wait() argument
607 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
609 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_reg_wait()
611 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
613 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_reg_wait()
615 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
618 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_reg_wait()
619 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_reg_wait()
622 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_reg_wait()
623 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_reg_wait()
626 amdgpu_ring_write(ring, mask); in jpeg_v2_0_dec_ring_emit_reg_wait()
629 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_vm_flush() argument
632 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in jpeg_v2_0_dec_ring_emit_vm_flush()
635 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in jpeg_v2_0_dec_ring_emit_vm_flush()
641 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); in jpeg_v2_0_dec_ring_emit_vm_flush()
644 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) in jpeg_v2_0_dec_ring_emit_wreg() argument
648 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_wreg()
651 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_wreg()
652 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_wreg()
655 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_wreg()
656 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_wreg()
659 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_wreg()
662 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) in jpeg_v2_0_dec_ring_nop() argument
666 WARN_ON(ring->wptr % 2 || count % 2); in jpeg_v2_0_dec_ring_nop()
669 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v2_0_dec_ring_nop()
670 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_nop()