Lines Matching refs:vmid

566 		entry->src_id, entry->ring_id, entry->vmid,  in gmc_v9_0_process_interrupt()
668 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, in gmc_v9_0_get_invalidate_req() argument
674 PER_VMID_INVALIDATE_REQ, 1 << vmid); in gmc_v9_0_get_invalidate_req()
708 uint8_t vmid, uint16_t *p_pasid) in gmc_v9_0_get_atc_vmid_pasid_mapping_info() argument
713 + vmid); in gmc_v9_0_get_atc_vmid_pasid_mapping_info()
736 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v9_0_flush_gpu_tlb() argument
755 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); in gmc_v9_0_flush_gpu_tlb()
756 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); in gmc_v9_0_flush_gpu_tlb()
758 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); in gmc_v9_0_flush_gpu_tlb()
772 1 << vmid); in gmc_v9_0_flush_gpu_tlb()
818 if (tmp & (1 << vmid)) in gmc_v9_0_flush_gpu_tlb()
858 int vmid, i; in gmc_v9_0_flush_gpu_tlb_pasid() local
912 for (vmid = 1; vmid < 16; vmid++) { in gmc_v9_0_flush_gpu_tlb_pasid()
914 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
919 gmc_v9_0_flush_gpu_tlb(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
922 gmc_v9_0_flush_gpu_tlb(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
934 unsigned vmid, uint64_t pd_addr) in gmc_v9_0_emit_flush_gpu_tlb() argument
939 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); in gmc_v9_0_emit_flush_gpu_tlb()
957 (hub->ctx_addr_distance * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
961 (hub->ctx_addr_distance * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
968 req, 1 << vmid); in gmc_v9_0_emit_flush_gpu_tlb()
982 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, in gmc_v9_0_emit_pasid_mapping() argument
993 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v9_0_emit_pasid_mapping()
995 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; in gmc_v9_0_emit_pasid_mapping()