629 	int vmid;  in gmc_v8_0_flush_gpu_tlb_pasid()  local
635 	for (vmid = 1; vmid < 16; vmid++) {  in gmc_v8_0_flush_gpu_tlb_pasid()
637 		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);  in gmc_v8_0_flush_gpu_tlb_pasid()
640 			WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb_pasid()
667 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v8_0_flush_gpu_tlb()  argument
671 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb()
675 					    unsigned vmid, uint64_t pd_addr)  in gmc_v8_0_emit_flush_gpu_tlb()  argument
679 	if (vmid < 8)  in gmc_v8_0_emit_flush_gpu_tlb()
680 		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;  in gmc_v8_0_emit_flush_gpu_tlb()
682 		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;  in gmc_v8_0_emit_flush_gpu_tlb()
686 	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_emit_flush_gpu_tlb()
691 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,  in gmc_v8_0_emit_pasid_mapping()  argument
694 	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);  in gmc_v8_0_emit_pasid_mapping()
1012 	u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);  in gmc_v8_0_vm_decode_fault()  local
1023 	       protections, vmid, pasid, addr,  in gmc_v8_0_vm_decode_fault()
1437 	u32 addr, status, mc_client, vmid;  in gmc_v8_0_process_interrupt()  local
1475 	vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,  in gmc_v8_0_process_interrupt()
1477 	if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)  in gmc_v8_0_process_interrupt()
1484 		info->vmid = vmid;  in gmc_v8_0_process_interrupt()